SI5040-D-GM Silicon Laboratories Inc, SI5040-D-GM Datasheet - Page 33

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SI5040-D-GM

Manufacturer Part Number
SI5040-D-GM
Description
IC TXRX XFP 10GBPS 32LGA
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of SI5040-D-GM

Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Si5040
11. Interrupt Functionality
Alarm Status bits (Register 9/137) are sampled by a
10 MHz clock to create the Interrupt Status bits
(Register 5/133). If the Interrupt Enable bit (Register 2,
bit 5) is a zero, all the Interrupt status bits are forced to
zero. The Alarm Status bits are always active regardless
of the state of the Interrupt Enable bit and the Interrupt
Mask bits. The Interrupt Mask bits (Register 4/132)
masks the Alarms Status bits from affecting the
corresponding Interrupt Status bit. Writing a zero to an
Interrupt Status bit forces that bit to a zero; however, if
the corresponding Alarm bit is active and the Interrupt
Mask bit is not set, the next 10 MHz clock cycle will
again cause the Interrupt Status bit to set. All of the
Interrupt Status bits are logically “NORed” together to
create the Interrupt bit (or pin16). Please refer to
Figure 23 for an illustration of the device interrupt tree.
The polarity of the Interrupt (pin 16) is active low.
Rev. 0.86
33

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