SI5040-D-GM Silicon Laboratories Inc, SI5040-D-GM Datasheet - Page 31

• Manufacturer Part Number: SI5040-D-GM
• Description: IC TXRX XFP 10GBPS 32LGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5040-D-GM

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The tpChkErrCnt register holds the error count from the
last completed time base if the checker is in a defined
time base mode; otherwise, in the infinite time base
setting, the current running error count is stored. An
interrupt is generated when the number of errors
exceeds the value loaded in the 8-bit tpTargetErr
register (receiver Register 47, transmitter Register 175).
The tpChkErr register holds the error count in an 8-bit
floating point format.
In order for the pattern generation/check function to
operate correctly, a timing source must be applied. A
valid
generation/check function can be any of the following:



A valid timing source for the transmitter pattern
generation/check function can be any of the following:



A reference clock with the device placed in lock-to-
reference mode.
Data applied at the RXDIN inputs from which a
recovered clock can be derived.
Data applied at the TD inputs from which a
recovered clock can be derived and with the device
placed in XFI loopback mode.
A reference clock with the device placed in lock-to-
reference mode.
Data applied at the TD inputs from which a
recovered clock can be derived.
Data applied at the RXDIN inputs from which a
recovered clock can be derived and with the device
placed in Looptime mode.
timing
source
for
the
receiver
pattern
Rev. 0.86
10. Serial Microcontroller Interface
Device control and status monitoring is supported with a
selectable I
controls which of the two serial formats is selected.
10.1. I
When configured in I
low), the control interface to the Si5040 is a 2-wire bus
for bidirectional communication. The bus consists of a
bidirectional serial data line (SD) and a serial clock input
(SCK). The SD pin may be configured as a CMOS
output or as an open drain output using Register 2, bit 4.
Fast mode operation is supported for transfer rates up
to 400 kbps as specified in the I
standard. A chip select pin is provided (SS) to address
the Si5040.
Figure 21 shows the command format for both read and
write access. Data is always sent MSB first. Table 2 on
page 6 and Table 3 on page 8 give the dc and ac
electrical parameters for the SCL and SDA I/Os,
respectively. The timing specifications and timing
diagram for the I
Specification standard (fast mode operation).
The device has two possible I
on the SSb pin setting. If the SSb pin is floating or
externally tied high, the device has an I
7d' 1000001. If the SSb pin is externally tied low, the
device has an I
applications that require two Si5040 devices connected
on the same I
accessed with a unique I
SSb pin setting.
Figure 22 illustrates how the I
configured and what the expected value is for the first
byte after the START condition. Note that the first byte
after the START condition could be either 82h or 83h
depending on whether it's a read or write. The first byte
after the START condition could be either 80h or 81h
depending on whether it is a read or write.
S
S
Slave Address
Slave Address
1 Read
2
Address auto incremented after each data read or write
Figure 21. I
C Interface
From master to slave
From slave to master
2
0
0
C or SPI-like interface. SPSEL (Pin 9)
A
A
2
Byte Address
C bus, each individual device can be
Byte Address
2
2
C bus can be found in the I
C address of 7d' 1000000. For
2
Write Command
Read Command
2
C control mode (pin SPSEL tied
C Command Format
A
A
0 Write
A – Acknowledge (SDA LOW)
S – START condition
P – STOP condition
2
S
C address depending on the
Slave Address
Data
2
C addresses depending
2
2
A
C address can be
C-Bus Specification
1
1
Data
A
Si5040
Data
2
C address of
A
A
P
Data
2
C-Bus
A
P
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