SI5040-D-GM Silicon Laboratories Inc, SI5040-D-GM Datasheet - Page 32

• Manufacturer Part Number: SI5040-D-GM
• Description: IC TXRX XFP 10GBPS 32LGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5040-D-GM

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si5040
10.2. SPI-Like Interface
When configured in SPI-like control mode (pin SPSEL
tied high), the control interface to the Si5040 is a 3-wire
interface
microcontrollers and bidirectional serial peripheral
devices. The interface consists of a clock input (SCK),
slave select input (SS), and serial data input/output
(SD). The SD pin may be configured as a CMOS output
or as an open drain output using Register 2, bit 4.
Data is transferred one byte at a time, with each register
access consisting of a pair of byte transfers. Figure 7
and Figure 8 on page 15 illustrate read and write/set
address operations on the SPI bus, and Table 9 on
page 14 gives the timing requirements for the interface.
Table 12 shows the SPI command format.
The first byte of the pair is the instruction byte. The "Set
Address" command writes the 8-bit address value that
will be used for the subsequent read or write.
32
Source: Fig 14 of I
By design, this bit in the I
is determined by the SSb pin.
1
Figure 22. Device I
modeled
0
0
2
C – Bus Specification Version 2.1
0
close
0
2
C address
0 X
to
2
C Address
Per I
either 1 for read or 0 for write.
commonly-available
2
C specification, this bit is
Rev. 0.86
The "Write" command writes data into the device based
on the address previously established, and the "Write/
Address Increment" command writes data into the
device and automatically increments the register
address for use on the subsequent command. The
"Read" command reads one byte of data from the
device, and the "Read/Address Increment" reads one
byte and increments the register address automatically.
The second byte of the pair is the address or data byte.
As shown in Figure 7 and Figure 8 on page 15, SS
should be held low during the entire two byte transfer.
Raising SS resets the internal state machine; so, SS
must be raised between each two byte transfers to
guarantee that the state machine will be reinitialized.
During a read operation, the SD becomes active on the
falling edge of SCK, and the 8-bit contents of the
register are driven out MSB first. The SD is high-
impedance on the rising edge of SS. During write
operations, data is driven into the Si5040 via the SD pin
MSB first. Data always transitions with the falling edge
of the clock and is latched on the rising edge.
The clock should return to a logic high when no transfer
is in progress. The Si5040 SPI-like interface supports
continuous clocking operation where SS is used to gate
two byte transfers.
00000000—Set Address
01000000—Write
01100000—Write/Address Increment
10000000—Read
10100000—Read/Address Increment
Table 12. SPI-Like Command Format
Instruction
Address/Dat
DDDDDDDD
DDDDDDDD
DDDDDDDD
DDDDDDDD
AAAAAAAA