SI5040-D-GM Silicon Laboratories Inc, SI5040-D-GM Datasheet - Page 35

• Manufacturer Part Number: SI5040-D-GM
• Description: IC TXRX XFP 10GBPS 32LGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5040-D-GM

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si5040
12. Programmable Power Down
Options
The Rx and Tx paths can be powered down
independently by programming RxPdn = 1 at Register
3, Bit 0 (Default = 0) or TxPdn = 1 at Register 131, Bit 0
(Default = 0), respectively. As long as both paths are not
powered down, all registers are still accessible. Any
values written to the registers of the powered-down path
will have no immediate effect but will take effect once
the path is powered back up and a recalibration is
initiated (Rx hardRecal at Register 8, Bit 3 or Tx
hardRecal at Register 136, Bit 3). Any read of registers
of the powered-down path will return garbage as there
is no VCO clock.
When both the Rx and Tx paths are powered down,
there is a special power up requirement that depends
upon the state of the SPSEL pin. If SPSEL is high, any
read or write access will wake up the device. The path
that was last powered down will be powered up first.
The other path can then be powered up by setting the
appropriate Pdn bit to a zero. Each side that is powered
up must have a hard recal performed to calibrate all
circuits (Rx hardRecal at Register 8, Bit 3, or Tx
hardRecal at Register 136, Bit 3).
2
If SPSEL is low (I
C mode), power up from both sides
powered down can only be accomplished by physically
removing VDD from the Si5040 and then re-applying
VDD. Of course, this will power up both sides of the
device, and a hard recal will automatically occur.
Note that interrupts must be masked or ignored during
power down and unmasked and cleared after the
recalibration.
Rev. 0.86
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