SI5040-D-GM Silicon Laboratories Inc, SI5040-D-GM Datasheet - Page 103

• Manufacturer Part Number: SI5040-D-GM
• Description: IC TXRX XFP 10GBPS 32LGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5040-D-GM

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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Revision 0.8 to Revision 0.85
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Updated definition of Proportional Slice Threshold to
show Threshold = 50% + sliceLvl/65536 x 100 in
Registers 21and 22/
Changed definition of Register 139, bit 4, from R/W
to R.
Clarified operation of fifoErr bit in the Register 4, bit
3.
Updated definition of Reserved bits in Registers 56
and 184, bits 5:3.
Reduced the input reference clock frequencies in
Table 5 from 712.5 and 178.125 MHz to 709.38 and
177.34 MHz, respectively.
Modified Detailed Block Diagram to show Slice_ADJ
controlling the Programmable Equalizer block.
Clarified definition of lolMode in Register 7 and 135,
bit 2.
Clarified description of Register 2, bit 4, as “SD pin
drive configuration”.
Changed Reserved bit (Register 2, bit 7) to support
configuration of RX_LOS pin as open drain output.
The default configuration register bit settings
changed to the following: Reg6[7:4] = 4h,
Reg134[7:4] = 4h, Reg138[3:1] = 111b,
Reg145[7:0] = 00h Reg154[7:2] = 1,
Reg155[5:0] = 8, Reg184[7:6] = 11b,
Reg56[7:6] = 11b, Reg85[7:5] = 111b.
Revision ID, Register 1 bits 7:4, changed from 2 to 3
decimal to reflect Rev D.
Updated Theta JA value in Table 11.
Deleted Note 4 from Table 7.
Updated "Acquisition Time" test condition (Register
68, bit3:0) in Table 3
Removed both Stressed Eye Jitter Tolerance and
Sinusoidal Jitter Tolerance from Table 3.
Corrected "OCIP2" typo in TXDOUT jitter test
conditions in Table 5.
Clarified jitter transfer peaking test condition in
Table 5.
Removed Note 2 from Table 5.
Changed definition of bits 7:6 in Register 56 to
Reserved.
Changed definition of bits 7:6 in Register 184 to
Reserved.
Updated mechanical ground pad dimension in
Table 14.
Updated package drawing in Figure 25.
Updated Table 14, “Package Diagram Dimensions,”
on page 100.
Rev. 0.86
Revision 0.85 to Revision 0.86
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Updated title on page 1.
Updated block diagram.
Changed pins 10 and 11 to NC.
Updated Typical Application Schematic (Section 3).
Clarified operation of each slice mode in section "5.5
Receiver Slice Control".
Updated Section "5.8. Receiver Loss of Lock (LOL)."
Added technical info on Rx SQM and Frequency
LOL; added info on dynamic register control and
acquisition time enhancement.
Added Section "5.11. Recommended Pre-Emphasis
on the RD Signal."
Updated Section 6.4. Transmitter Loss of Lock
(LOL). Added technical info on Tx SQM and
Frequency LOL; added info on dynamic register
control and acquisition time enhancement.
Removed section "6.7.4. Low Bandwidth Jitter
Attenuation Mode (Mode 3)" and support for mode 3.
Updated section "7. Loopback Modes" with technical
info on XFI and Lineside loopback modes.
Updated Section "12. Programmable Power Down
Options."
Added register summary and definitions in Section
13 for Registers 77, 98, 106-107, 205, and 226.
Removed Section “18. Recommended Crystal
Resonators” on page 94.
Max power/current now specified for Mode 0 instead
of Mode 3.
Si5040
103