SI5040-D-GM Silicon Laboratories Inc, SI5040-D-GM Datasheet - Page 27

• Manufacturer Part Number: SI5040-D-GM
• Description: IC TXRX XFP 10GBPS 32LGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5040-D-GM

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6. Transmitter
The Si5040 transmitter includes an XFI-compliant,
fixed-equalizer CDR for recovery of clock and data from
the XFI channel (TD inputs), pattern generation and
checking function (see “6.3. Clock and Data Recovery
(CDR)”), transmit FIFO, and jitter-attenuating clock
multiplier unit.
6.1. Transmitter Loss-of-Signal Alarm
The Si5040 transmitter generates a loss-of-signal alarm
when the TD input signal fails to meet the selected
programmable condition for Transmit Loss of Signal.
The programmable LOS mode is controlled in the
TxLosCtrl register (Register 138). The available modes
are Digital Loss of Signal (DLOS) and Signal Quality
Monitor (SQM). The state of LOS is reflected in the LOS
bit in the TxLosStatus register (Register 139). LOS may
also be configured to generate an interrupt. The status
of the LOS interrupt bit may be read in the TxintStatus
register (Register 133). The status of the various LOS
modes
(Register 139).
A DLOS alarm occurs when the bit stream on the TD
input contains a run length of ones or zeroes greater
than the value loaded in the TxdLosAssertThresh
register (Register 145). dLos will remain asserted until
the bit stream shows activity for a time greater than that
loaded
(Register 146).
An SQM alarm occurs when the TD input signal quality
falls
(Register 154). The Signal Quality Monitor measures
the magnitude of the horizontal eye opening of the
received signal. The SQM value can be read from the
TxsqmValue register (Register 153). An SQM alarm will
assert if the TxsqmEn bit has been set in the
TxSqmConfig register (Register 154). SQM hysteresis
is
(Register 155).
The transmitter may be programmed to cause the
following events on an LOS condition:
1. Disable (squelch) the transmitter data output
2. Generate a clock pattern at the transmit data output
(TXDOUT) (Register 156).
(TXDOUT) (Register 156).
set
(LOS)
below
is
in
in
stored
the
the
the
value
TxsqmDeassertThresh
in
TxdLOSClearThresh
the
loaded
TxLosStatus
in
TxSqmThresh
register
register
register
Rev. 0.86
6.2. Transmit Equalizer
The Tx equalizer is a passive, fixed-gain equalizer
based on the inverse response of the XFI channel. The
equalizer attenuates the low-frequency components of
the input signal to compensate for the high-frequency
losses through the XFI channel. The overall frequency
response through the XFI channel and the equalizer
should be essentially flat.
6.3. Clock and Data Recovery (CDR)
The Si5040 integrates a CDR to recover the clock and
data from the signal applied to the TD input. The CDR
may be operated with or without an external reference
clock. Reference and referenceless operation is
programmed in the TxCalConfig register (Register 136).
If a reference clock is applied, the CDR may be forced
to lock to the reference clock in the event that a loss of
signal occurs. This option is programmed in the
TxConfig register (Register 135).
6.4. Transmitter Loss of Lock (LOL)
Transmitter LOL functions in different ways depending
on whether the transmitter is operating in reference or
referenceless mode. By default (uselolmode Register
135,
referenceless mode, and Frequency-based LOL is used
in reference mode. However, in reference mode, either
SQM or Frequency LOL can be used by setting Register
135, Bits 2 and 3, to the appropriate values.
6.4.1. SQM LOL
When the VCO is configured to calibrate without a
reference clock (VCOCAL[1:0] = 01 binary), the default
values of register 135[3:2] will cause the LOL method to
be SQMLOL. Just as in the receiver (see "5.8.1. SQM
LOL" on page 23), the SQMLOL method compares an
internal jitter measure to the sqmLOLThresh; however,
the Tx sqmLOLThresh value must not be modified.
When the internal jitter measure is greater than the
sqmLOLThresh,
deasserted when the jitter measure is less than the
sqmLOLThresh.
6.4.1.1. Dynamic Register Control
The dynamic control of TxLoopFAcq (Register 226) is
required to ensure the locking performance of the CDR.
For
TxLoopFAcq be set to 98h when Tx LOL is asserted
and to 00h when Tx LOL is deasserted. Only the default
value and the value given above are supported for
Register 226. Any read back of this register will not
necessarily return 98h.
In addition, for proper LOL performance, TxPDGainAcq
(Register 205) must be written once to 0Dh after power
is applied or a SW reset is implemented.
all
Bit
applications,
3 = 0),
TXLOL
SQM-based
it
is
is
asserted.
recommended
LOL
Si5040
is
TxLOL
used
that
27
in
is