R5F61668RD50FPV Renesas Electronics America, R5F61668RD50FPV Datasheet - Page 964
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R5F61668RD50FPV
Manufacturer Part Number
R5F61668RD50FPV
Description
MCU 3V 1024K I-TEMP 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668RN50FPV.pdf
(1506 pages)
Specifications of R5F61668RD50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61668RD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 19 Serial Communication Interface (SCI, IrDA, CRC)
19.6.2
Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize
the SCI as described in a sample flowchart in figure 19.18. When the operating mode, transfer
format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When
the TE bit is cleared to 0, the TDRE flag is set to 1. However, clearing the RE bit to 0 does not
initialize the RDRF, PER, FER, and ORER flags, or RDR.
Rev. 2.00 Sep. 24, 2008 Page 930 of 1468
REJ09B0412-0200
SCI Initialization (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only)
Note: In simultaneous transmit and receive operations, the TE and RE bits should both
Clear TE and RE bits in SCR to 0
set RIE, TIE, TEIE, and MPIE bits
Set TE or RE bit in SCR to 1, and
Set corresponding bit in ICR to 1
Set CKE1 and CKE0 bits in SCR
Set data transfer format in
be cleared to 0 or set to 1 simultaneously.
(TE and RE bits are 0)
1-bit interval elapsed?
Set value in BRR
Start initialization
SMR and SCMR
<Transfer start>
Figure 19.18 Sample SCI Initialization Flowchart
Yes
Wait
No
[5]
[2]
[3]
[1]
[4]
[1]
[2] Set the clock selection in SCR. Be sure
[3] Set the data transfer format in SMR and
[4] Write a value corresponding to the bit
[5] Wait at least one bit interval, then set
to clear bits RIE, TIE, TEIE, and MPIE,
and bits TE and RE, to 0.
SCMR.
rate to BRR. This step is not necessary
if an external clock is used.
the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE TEIE, and MPIE
bits. Setting the TE and RE bits enables
the TxD and RxD pins to be used.
Set the bit in ICR for the corresponding
pin when receiving data or using an
external clock.
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