R5F61668RD50FPV Renesas Electronics America, R5F61668RD50FPV Datasheet - Page 1127

• Manufacturer Part Number: R5F61668RD50FPV
• Description: MCU 3V 1024K I-TEMP 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RD50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

For details on the procedure in cases where point 1 or 3 is applicable, see figure 22.11
22.7.4
This LSI's analog input is designed so that the conversion accuracy is guaranteed for an input
signal for which the signal source impedance is 5 kΩ or less. This specification is provided to
enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the
sampling time; if the sensor output impedance exceeds 5 kΩ, charging may be insufficient and it
may not be possible to guarantee the A/D conversion accuracy. However, if a large capacitance is
Figure 22.11 Procedure for Changing the Mode When the Setting for Activation by an
Only execute switching from activation by an external trigger to prohibition of external
triggers or changing of the scan mode (ADSTLCR and SCANE bits) when the setting for
activation by an external trigger is in use after external trigger input has been disabled.
External trigger input can be disabled by writing specific values to bits TRGS1, TRGS0, and
EXTRGS.
Notes: 1.
Permissible Signal Source Impedance
Change the setting by an
Change the scan mode
ADCR.EXTRGS = 1
External trigger
ADCR.TRGS1 = 0
ADCR.TRGS0 = 0
ADCSR.ADST = 0
2.
external trigger*
(External trigger
disabled)*
halted?
For details, see section 14.3.4, Timer Interrupt Enable Register (TIER).
The TTGE bit in TIER of the TPU unit must be held 0.
Rewrite TRGS1, TRGS0, and EXTRGS bits in ADCR simultaneously (in byte unit)
Unit 0
No
2
2
External Trigger is in Use
Yes
Change the setting by an
Change the scan mode
Rev. 2.00 Sep. 24, 2008 Page 1093 of 1468
ADCR.EXTRGS = 1
ADCR.TRGS1 = 0
ADCR.TRGS0 = 1
ADCSR.ADST = 0
External trigger
external trigger*
(External trigger
disabled)*
halted?
Unit 1
No
1
, *
2
2
Section 22 A/D Converter
Yes
REJ09B0412-0200