R5F61668RD50FPV Renesas Electronics America, R5F61668RD50FPV Datasheet - Page 82
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R5F61668RD50FPV
Manufacturer Part Number
R5F61668RD50FPV
Description
MCU 3V 1024K I-TEMP 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668RN50FPV.pdf
(1506 pages)
Specifications of R5F61668RD50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61668RD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 82 of 1506
- Download datasheet (9Mb)
Section 2 CPU
2.6
The H8SX CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword)
data.
Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte
operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit
BCD data.
2.6.1
Figure 2.12 shows the data formats in general registers.
Rev. 2.00 Sep. 24, 2008 Page 48 of 1468
REJ09B0412-0200
Data Formats
General Register Data Formats
1-bit data
1-bit data
4-bit BCD data
4-bit BCD data
Byte data
Byte data
Word data
Word data
Longword data
MSB
MSB
[Legend]
ERn:
En:
Rn:
RnH:
15
31
General register ER
General register E
General register R
General register RH
Figure 2.12 General Register Data Formats
En
RnH
RnL
RnH
RnL
RnH
RnL
Rn
En
ERn
LSB
16
0
RnL:
MSB:
LSB:
MSB
MSB
7
7
7
15
15
7 6 5 4 3 2 1 0
Upper
Don't care
Don't care
Don't care
General register RL
Most significant bit
Least significant bit
4 3
Lower
LSB
Rn
0
0
0
MSB
7
7
7
7 6 5 4 3 2 1 0
Upper
Don't care
Don’t care
Don't care
4 3
Lower
LSB
LSB
LSB
0
0
0
0
0
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