R5F61668RD50FPV Renesas Electronics America, R5F61668RD50FPV Datasheet - Page 426
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
R5F61668RD50FPV
Manufacturer Part Number
R5F61668RD50FPV
Description
MCU 3V 1024K I-TEMP 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668RN50FPV.pdf
(1506 pages)
Specifications of R5F61668RD50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61668RD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 426 of 1506
- Download datasheet (9Mb)
Section 10 DMA Controller (DMAC)
Rev. 2.00 Sep. 24, 2008 Page 392 of 1468
REJ09B0412-0200
Bit
7
6
5
4, 3
Bit Name
DTF1
DTF0
DTA
Initial
Value
0
0
0
All 0
R/W
R/W
R/W
R/W
R
Description
Data Transfer Factor 1 and 0
Select a DMAC activation source. When the on-chip
peripheral module setting is selected, the interrupt
source should be selected by DMRSR. When the
external request setting is selected, the sampling
method should be selected by the DREQS bit.
00: Auto request (cycle stealing)
01: Auto request (burst access)
10: On-chip module interrupt
11: External request
Data Transfer Acknowledge
This bit is valid in DMA transfer by the on-chip module
interrupt source. This bit enables or disables to clear the
source flag selected by DMRSR.
0: To clear the source in DMA transfer is disabled.
1: To clear the source in DMA transfer is enabled.
Reserved
These bits are always read as 0 and cannot be
modified.
Since the on-chip module interrupt source is not
cleared in DMA transfer, it should be cleared by the
CPU or DTC transfer.
Since the on-chip module interrupt source is cleared
in DMA transfer, it does not require an interrupt by the
CPU or DTC transfer.
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