R5F61668RD50FPV Renesas Electronics America, R5F61668RD50FPV Datasheet - Page 230
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R5F61668RD50FPV
Manufacturer Part Number
R5F61668RD50FPV
Description
MCU 3V 1024K I-TEMP 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668RN50FPV.pdf
(1506 pages)
Specifications of R5F61668RD50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61668RD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 230 of 1506
- Download datasheet (9Mb)
Section 9 Bus Controller (BSC)
Note:
Rev. 2.00 Sep. 24, 2008 Page 196 of 1468
REJ09B0412-0200
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
*
Bit Name
CSXH7
CSXH6
CSXH5
CSXH4
CSXH3
CSXH2
CSXH1
CSXH0
CSXT7
CSXT6
CSXT5
CSXT4
CSXT3
CSXT2
CSXT1
CSXT0
In burst ROM interface, the CSXTn settings are ignored during read accesses by the
CPU and EXDMAC cluster transfer.
Initial
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
CS and Address Signal Assertion Period Control 1
These bits specify whether or not the Th cycle is to be
inserted (see figure 9.3). When an area for which bit
CSXHn is set to 1 is accessed, one Th cycle, in which
the CSn and address signals are asserted, is inserted
before the normal access cycle.
0: In access to area n, the CSn and address assertion
1: In access to area n, the CSn and address assertion
(n = 7 to 0)
CS and Address Signal Assertion Period Control 2
These bits specify whether or not the Tt cycle is to be
inserted (see figure 9.3). When an area for which bit
CSXTn is set to 1 is accessed, one Tt cycle, in which
the CSn and address signals are retained, is inserted
after the normal access cycle.
0: In access to area n, the CSn and address assertion
1: In access to area n, the CSn and address assertion
(n = 7 to 0)
period (Th) is not extended
period (Th) is extended
period (Tt) is not extended
period (Tt) is extended
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