R5F61668RD50FPV Renesas Electronics America, R5F61668RD50FPV Datasheet - Page 1319
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R5F61668RD50FPV
Manufacturer Part Number
R5F61668RD50FPV
Description
MCU 3V 1024K I-TEMP 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668RN50FPV.pdf
(1506 pages)
Specifications of R5F61668RD50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61668RD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 1319 of 1506
- Download datasheet (9Mb)
Section 28 Power-Down Modes
28.12
Usage Notes
28.12.1 I/O Port Status
In software standby mode or deep software standby mode, the I/O port states are retained.
Therefore, there is no reduction in current drawn due to output currents when high-level signals
are being output.
28.12.2 Current Consumption during Oscillation Settling Standby Period
Current consumption increases during the oscillation settling standby period.
28.12.3 Module Stop State of EXDMAC, DMAC, or DTC
Depending on the operating state of the EXDMAC, DMAC, and DTC, bits MSTPA14,
MSTPA13, and MSTPA12 may not be set to 1, respectively. The module stop state setting for the
EXDMAC, DMAC, or DTC should be carried out only when the EXDMAC, DMAC, or DTC is
not activated.
For details, refer to section 10, DMA Controller (DMAC), section 11, EXDMA Controller
(EXDMAC), and section 12, Data Transfer Controller (DTC).
28.12.4 On-Chip Peripheral Module Interrupts
Relevant interrupt operations cannot be performed in a module stop state. Consequently, if the
module stop state is entered when an interrupt has been requested, it will not be possible to clear
the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore be
disabled before entering a module stop state.
28.12.5 Writing to MSTPCRA, MSTPCRB, and MSTPCRC
MSTPCRA, MSTPCRB, and MSTPCRC should only be written to by the CPU.
Rev. 2.00 Sep. 24, 2008 Page 1285 of 1468
REJ09B0412-0200
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