R5F61668RD50FPV Renesas Electronics America, R5F61668RD50FPV Datasheet - Page 396

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R5F61668RD50FPV

Manufacturer Part Number
R5F61668RD50FPV
Description
MCU 3V 1024K I-TEMP 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61668RD50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61668RD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 Bus Controller (BSC)
9.13.3
Figures 9.102 and 9.103 show the timing of transition to the bus released state.
Rev. 2.00 Sep. 24, 2008 Page 362 of 1468
REJ09B0412-0200
[1] A low level of the BREQ signal is sampled at the rising edge of the Bφ signal.
[2] The bus control signals are driven high at the end of the external space access cycle. It takes two cycles or
[3] The BACK signal is driven low, releasing bus to the external bus master.
[4] The BREQ signal state sampling is continued in the external bus released state.
[5] A high level of the BREQ signal is sampled.
[6] The external bus released cycles are ended one cycle after the BREQ signal is driven high.
[7] When the external space is accessed by an internal bus master during external bus released while the BREQOE
[8] Normally the BREQO signal goes high at the rising edge of the BACK signal.
Figure 9.102 Bus Released State Transition Timing (SRAM Interface is Not Used)
Address bus
Data bus
CSn
AS
RD
LHWR, LLWR
BREQ
BACK
BREQO
more after the low level of the BREQ signal is sampled.
bit is set to 1, the BREQO signal goes low.
Transition Timing
External space
access cycle
[1]
T
1
T
2
[2]
[3]
[4]
External bus released state
[7]
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
[5]
[8]
[6]
CPU cycle

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