R5F61668RD50FPV Renesas Electronics America, R5F61668RD50FPV Datasheet - Page 1085
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R5F61668RD50FPV
Manufacturer Part Number
R5F61668RD50FPV
Description
MCU 3V 1024K I-TEMP 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668RN50FPV.pdf
(1506 pages)
Specifications of R5F61668RD50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61668RD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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21.4.2
In I
data, and the slave device return an acknowledge signal. Figures 21.5 and 21.6 show the operating
timings in master transmit mode. The transmission procedure and operations in master transmit
mode are described below.
1. Set the ICR bit in the corresponding register to 1. Set the ICE bit in ICCRA to 1. Set the WAIT
2. Read the BSSY flag in ICCRB to confirm that the bus is free. Set the MST and TRS bits in
3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte shows
4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1
5. The transmit data after the second byte is written to ICDRT every time TDRE is set.
6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last
7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
2
bit in ICMR and the CKS3 to CKS0 bits in ICCRA to 1. (initial setting)
ICCRA to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using the MOV
instruction. (The start condition is issued.) This generates the start condition.
the slave address and R/W) to ICDRT. After this, when TDRE is automatically cleared to 0,
data is transferred from ICDRT to ICDRS. TDRE is set again.
at the rising of the ninth transmit clock pulse. Read the ACKBR bit in ICIER to confirm that
the slave device has been selected. Then, write the second byte data to ICDRT. When ACKBR
is 1, the slave device has not been acknowledged, so issue a stop condition. To issue the stop
condition, write 0 to BBSY and SCP using the MOV instruction. SCL is fixed to a low level
until the transmit data is prepared or the stop condition is issued.
byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR is 1) from the
receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or
NACKF.
C bus format master transmit mode, the master device outputs the transmit clock and transmit
Master Transmit Operation
Rev. 2.00 Sep. 24, 2008 Page 1051 of 1468
Section 21 I
2
C Bus Interface 2 (IIC2)
REJ09B0412-0200
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