R5F61668RD50FPV Renesas Electronics America, R5F61668RD50FPV Datasheet - Page 804
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
R5F61668RD50FPV
Manufacturer Part Number
R5F61668RD50FPV
Description
MCU 3V 1024K I-TEMP 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668RN50FPV.pdf
(1506 pages)
Specifications of R5F61668RD50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61668RD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.10.7 Conflict between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the
buffer operation will be the write data.
Figure 14.50 shows the timing in this case.
14.10.8 Conflict between TGR Read and Input Capture
If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read
will be the data after input capture transfer.
Figure 14.51 shows the timing in this case.
Rev. 2.00 Sep. 24, 2008 Page 770 of 1468
REJ09B0412-0200
Figure 14.50 Conflict between Buffer Register Write and Compare Match
Pφ
Address
Write
Compare match
signal
Buffer register
TGR
Pφ
Address
Read
Input capture
signal
TGR
Internal data
bus
Figure 14.51 Conflict between TGR Read and Input Capture
X
TGR write cycle
TGR read cycle
TGR address
N
T
Buffer register
T
1
1
address
T
T
2
M
2
M
M
Data written to buffer register
M
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