R5F61668RD50FPV Renesas Electronics America, R5F61668RD50FPV Datasheet - Page 1095
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
R5F61668RD50FPV
Manufacturer Part Number
R5F61668RD50FPV
Description
MCU 3V 1024K I-TEMP 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668RN50FPV.pdf
(1506 pages)
Specifications of R5F61668RD50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61668RD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 1095 of 1506
- Download datasheet (9Mb)
Note: 1.
2.
No
No
No
Set ACKBT = 0 (ICIER)
Set ACKBT = 1 (ICIER)
Set RCVD = 1 (ICCRA)
Set RCVD = 0 (ICCRA)
Do not generate an interrupt during steps [1] to [3].
For one-byte reception, steps [2] to [6] do not need to be executed. After step [1], execute step [7].
In step [8], read ICDRR (dummy read).
Set TRS = 0 (ICCRA)
Set MST = 0 (ICCRA)
Master receive mode
Dummy read ICDRR
Read RDRF in ICSR
Write BBSY = 0 and
Clear TEND in ICSR
Clear TDRE in ICSR
Clear STOP in ICSR
Read STOP in ICSR
Dummy read ICSR
Read ICDRR
Read ICDRR
Read ICDRR
RDRF = 1?
receive -1?
RDRF = 1?
STOP = 1?
Figure 21.15 Sample Flowchart for Master Receive Mode
SCP = 0
Last
End
Yes
Yes
Yes
No
Yes
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Clear the STOP flag
[11] Issue the stop condition
[12] Wait for the creation of stop condition
[13] Read the receive data of the last byte
[14] Clear RCVD to 0
[15] Set to slave receive mode
Clear TEND, set to master receive mode, then clear TDRE*
Set acknowledge to the transmitting device*
Dummy read ICDRR*
Wait for 1 byte of data to be received*
Check if (last receive -1)*
Read the receive data*
Set acknowledge of the last byte. Disable continuous reception
(RCVD = 1).*
Read receive data of (last byte -1).*
Wait for the last byte to be received
2
Rev. 2.00 Sep. 24, 2008 Page 1061 of 1468
1
*
2
2
2
Section 21 I
2
2
2
C Bus Interface 2 (IIC2)
1
*
2
REJ09B0412-0200
1
*
2
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