R5F61668RD50FPV Renesas Electronics America, R5F61668RD50FPV Datasheet - Page 552
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R5F61668RD50FPV
Manufacturer Part Number
R5F61668RD50FPV
Description
MCU 3V 1024K I-TEMP 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668RN50FPV.pdf
(1506 pages)
Specifications of R5F61668RD50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61668RD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 11 EXDMA Controller (EXDMAC)
(4)
Figure 11.37 shows an example of single address mode transfer activated by the EDREQ pin low
level.
EDREQ pin sampling is performed in each cycle starting at the next rise of Bφ after the end of the
DTE bit write cycle.
When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the
EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated
within the EXDMAC, the request is cleared. After the end of the single cycle, acceptance resumes
and EDREQ pin low level sampling is performed again. This sequence of operations is repeated
until the end of the transfer.
Rev. 2.00 Sep. 24, 2008 Page 518 of 1468
REJ09B0412-0200
Bφ
EDREQ
Address bus
EDACK
EXDMA control
Channel
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of Bφ, and request is held.
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] EXDMA cycle starts.
[4], [7] Acceptance is resumed after completion of single cycle.
(As in [1], EDREQ pin low level is sampled at rise of Bφ, and request is held.)
EDREQ Pin Low Level Activation Timing
Figure 11.37 Example of Single Address Mode Transfer Activated
Idle
[1]
Request
Minimum 3 cycles
release
[2]
Bus
Request clearance period
by EDREQ Pin Low Level
Single
[3]
EXDMA single
Transfer destination
Transfer source/
Idle
Acceptance resumed
[4]
Minimum 3 cycles
Request
[5]
release
Bus
Request clearance period
Single
[6]
EXDMA single
Transfer destination
Transfer source/
Acceptance resumed
Idle
[7]
release
Bus
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