R5F61668RD50FPV Renesas Electronics America, R5F61668RD50FPV Datasheet - Page 314
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R5F61668RD50FPV
Manufacturer Part Number
R5F61668RD50FPV
Description
MCU 3V 1024K I-TEMP 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668RN50FPV.pdf
(1506 pages)
Specifications of R5F61668RD50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61668RD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 9 Bus Controller (BSC)
9.10
In this LSI, area 2 in the external space can be used as the DRAM interface space. Up to 8 Mbytes
of DRAM is directly connected via the DRAM interface.
9.10.1
Area 2 can be specified as the DRAM space by the DRAME and DTYPE bits in DRAMCR.
Table 9.20 lists the relationship among the DRAME and DTYPE bits and area 2 interfaces.
The bus settings of the DRAM space such as bus width and wait cycle number depend on area 2
settings.
Table 9.20 Relationship Among DRAME and DTYPE and Area 2 Interfaces
[Legend]
×: Don't care
9.10.2
A Row address and a column address are multiplexed in the DRAM space. Select the number of
row address bits to be shifted with bits MXC1 and MXC0 in DRAMCR. Table 9.21 lists the
relationship among bits MXC1 and MXC0 and shifted bit number.
Table 9.21 Relationship Among MXC1 and MXC0 and Shifted Bit Count
Rev. 2.00 Sep. 24, 2008 Page 280 of 1468
REJ09B0412-0200
DRAME
0
1
1
MXC1
DRAMCR
0
0
1
1
MXC0
0
1
0
1
DRAM Interface
Setting DRAM Space
Address Multiplexing
8 bits
9 bits
10 bits
11 bits
Shit Bit
Count
DTYPE
×
0
1
Data Bus
Width
8/16 bits
8/16 bits
8/16 bits
8/16 bits
Address
Row address
Column address
Row address
Column address
Row address
Column address
Row address
Column address
Area 2 Interface
Basic bus space (initial state)/byte-control SRAM space
DRAM space
SDRAM space
A27 to A18
A23 to A18
A23 to A18
A23 to A18
A23 to A18
A23 to A18
A23 to A18
A23 to A18
A23 to A18
A17 A16 A15 A14 A13 A12 A11 A10
A17
A17 A16 A15 A14 A13 A12 A11 A10
A17
A17 A16 A15 A14 A13 A12 A11 A10
A17
A17 A16 A15 A14 A13 A12 A11 A10
A17
A17 A16 A15 A14 A13 A12 A11 A10
-
-
-
-
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
-
-
-
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
-
-
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
-
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
External Address Pin
A9
A9
A9
A9
A9
A8
A8
A8
A8
A8
A7
A7
A7
A7
A7
A6
A6
A6
A6
A6
A5
A5
A5
A5
A5
A4
A4
A4
A4
A4
A3
A3
A3
A3
A3
A2
A2
A2
A2
A2
A1
A9
A1
A1
A1
A1
A8
A0
A0
A0
A9
A0
A0
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