R5F61668RD50FPV Renesas Electronics America, R5F61668RD50FPV Datasheet - Page 912
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R5F61668RD50FPV
Manufacturer Part Number
R5F61668RD50FPV
Description
MCU 3V 1024K I-TEMP 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668RN50FPV.pdf
(1506 pages)
Specifications of R5F61668RD50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61668RD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 19 Serial Communication Interface (SCI, IrDA, CRC)
Note:
Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1):
Rev. 2.00 Sep. 24, 2008 Page 878 of 1468
REJ09B0412-0200
Bit
1
0
Bit
7
6
5
4
*
Bit Name
CKS1
CKS0
Bit Name
GM
BLK
PE
O/E
Available in SCI_0, 1, 2, and 4 only. Setting is prohibited in SCI_5 and SCI_6.
Initial
Value
0
0
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Clock Select 1, 0
These bits select the clock source for the baud rate
generator.
00: Pφ clock (n = 0)
01: Pφ/4 clock (n = 1)
10: Pφ/16 clock (n = 2)
11: Pφ/64 clock (n = 3)
For the relation between the settings of these bits and the
baud rate, see section 19.3.9, Bit Rate Register (BRR).
n is the decimal display of the value of n in BRR (see
section 19.3.9, Bit Rate Register (BRR)).
Description
GSM Mode
Setting this bit to 1 allows GSM mode operation. In GSM
mode, the TEND set timing is put forward to 11.0 etu from
the start and the clock output control function is
appended. For details, see sections 19.7.6, Data
Transmission (Except in Block Transfer Mode) and
19.7.8, Clock Output Control (Only SCI_0, 1, 2, and 4).
Setting this bit to 1 allows block transfer mode operation.
For details, see section 19.7.3, Block Transfer Mode.
Parity Enable (valid only in asynchronous mode)
When this bit is set to 1, the parity bit is added to transmit
data before transmission, and the parity bit is checked in
reception. Set this bit to 1 in smart card interface mode.
Parity Mode (valid only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity
1: Selects odd parity
For details on the usage of this bit in smart card interface
mode, see section 19.7.2, Data Format (Except in Block
Transfer Mode).
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