R5F61668RD50FPV Renesas Electronics America, R5F61668RD50FPV Datasheet - Page 1073
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
R5F61668RD50FPV
Manufacturer Part Number
R5F61668RD50FPV
Description
MCU 3V 1024K I-TEMP 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668RN50FPV.pdf
(1506 pages)
Specifications of R5F61668RD50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61668RD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 1073 of 1506
- Download datasheet (9Mb)
21.3.2
ICCRB issues start/stop condition, manipulates the SDA pin, monitors the SCL pin, and controls
reset in the I
Bit
7
6
5
4
Bit
Bit Name
Initial Value
R/W
I
2
Bit Name
BBSY
SCP
SDAO
C Bus Control Register B (ICCRB)
2
C control module.
BBSY
R/W
7
0
Initial
Value
0
1
1
1
SCP
R/W
6
1
R/W
R/W
R/W
R
R/W
SDAO
R
5
1
Description
Bus Busy
This bit indicates whether the I
released and to issue start and stop conditions in
master mode. This bit is set to 1 when the SDA level
changes from high to low under the condition of SCL =
high, assuming that the start condition has been
issued. This bit is cleared to 0 when the SDA level
changes from low to high under the condition of SDA =
high, assuming that the stop condition has been
issued. Follow this procedure also when re-transmitting
a start condition. To issue a start or stop condition, use
the MOV instruction.
Start/Stop Condition Issue
This bit controls the issuance of start or stop condition
in master mode.
To issue a start condition, write 1 to BBSY and 0 to
SCP. A re-transmit start condition is issued in the same
way. To issue a stop condition, write 0 to BBSY and 0
to SCP. This bit is always read as 1. If 1 is written, the
data is not stored.
This bit monitors the output level of SDA.
0: When reading, the SDA pin outputs a low level
1: When reading the SDA pin outputs a high level
Reserved
The write value should always be 1.
R/W
4
1
SCLO
R
3
1
Rev. 2.00 Sep. 24, 2008 Page 1039 of 1468
Section 21 I
2
1
2
C bus is occupied or
2
IICRST
C Bus Interface 2 (IIC2)
R/W
1
0
REJ09B0412-0200
0
1
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