R5F61668RD50FPV Renesas Electronics America, R5F61668RD50FPV Datasheet - Page 525
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R5F61668RD50FPV
Manufacturer Part Number
R5F61668RD50FPV
Description
MCU 3V 1024K I-TEMP 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668RN50FPV.pdf
(1506 pages)
Specifications of R5F61668RD50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61668RD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 525 of 1506
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11.5.4
There are two bus modes: cycle steal mode and burst mode.
For auto-request activation, either cycle steal mode or burst mode can be selected by the DTF0 bit
in EDMDR. When the activation source is an external request, cycle steal mode is used.
(1)
In cycle steal mode, the EXDMAC releases the bus mastership at the end of each transfer of a
transfer unit (byte, word, longword, one block size, or one cluster size). If there is a subsequent
transfer request, the EXDMAC takes back the bus mastership, performs another transfer-unit
transfer, and then releases the bus mastership again at the end of the transfer. This procedure is
repeated until the transfer end condition is satisfied.
If a transfer request occurs in another channel during EXDMA transfer, the bus mastership is
temporarily released for another bus master, then transfer is performed on the channel for which
the transfer request was issued. For details on the operation when there are transfer requests for a
number of channels, see section 11.5.8, Channel Priority Order.
Figure 11.13 shows an example of the timing in cycle steal mode. The transfer conditions are as
follows:
• Address mode: Single address mode
• Sampling method on the EDREQ pin: Low level sensing
• CPU internal bus master is operating in external space
Cycle Steal Mode
Bus Mode
EDREQ
EDRAK
Bus cycle
Figure 11.13 Example of Timing in Cycle Steal Mode
CPU
CPU
Bus mastership returned temporarily to CPU
EXDMAC
CPU
Rev. 2.00 Sep. 24, 2008 Page 491 of 1468
Section 11 EXDMA Controller (EXDMAC)
EXDMAC
CPU
REJ09B0412-0200
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