R5F61668RD50FPV Renesas Electronics America, R5F61668RD50FPV Datasheet - Page 582
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R5F61668RD50FPV
Manufacturer Part Number
R5F61668RD50FPV
Description
MCU 3V 1024K I-TEMP 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668RN50FPV.pdf
(1506 pages)
Specifications of R5F61668RD50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61668RD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 11 EXDMA Controller (EXDMAC)
11.7
The operation for ending EXDMA transfer depends on the transfer end conditions. When
EXDMA transfer ends, the DTE bit and the ACT bit in EDMDR change from 1 to 0, indicating
that EXDMA transfer has ended.
(1)
When the value of EDTCR changes from 1, 2, or 4 to 0, EXDMA transfer ends on the
corresponding channel. The DTE bit in EDMDR is cleared to 0, and the DTIF bit in EDMDR is
set to 1. If the DTIE bit in EDMDR is set to 1 at this time, a transfer end interrupt request is
generated by the transfer counter. EXDMA transfer does not end if the EDTCR value has been 0
since before the start of transfer.
(2)
When the following conditions are satisfied while the TSEIE bit in EDMDR is set to 1, a transfer
size error occurs and an EXDMA transfer is terminated. At this time, the DTE bit in EDMDR is
cleared to 0 and the ESIF bit in EDMDR is set to 1.
• In normal transfer mode and repeat transfer mode, when the next transfer is requested while a
• In block transfer mode, when the next transfer is requested while a transfer is disabled due to
• In cluster transfer mode, when the next transfer is requested while a transfer is disabled due to
When the TSEIE bit in EDMDR is cleared to 0, data is transferred until the EDTCR value reaches
0. A transfer size error is not generated. Operation in each transfer mode is described below.
• In normal transfer mode and repeat mode, when the EDTCR value is less than the data access
• In block transfer mode, when the EDTCR value is less than the block size, the specified size of
• In cluster transfer mode, when the EDTCR value is less than the cluster size, the specified size
Rev. 2.00 Sep. 24, 2008 Page 548 of 1468
REJ09B0412-0200
transfer is disabled due to the EDTCR value less than the data access size.
the EDTCR value less than the block size.
the EDTCR value less than the cluster size.
size, data is transferred in bytes.
data in EDTCR is transferred instead of transferring the block size of data. When the EDTCR
value is less than the data access size, data is transferred in bytes.
of data in EDTCR is transferred instead of transferring the cluster size of data. When the
EDTCR value is less than the data access size, data is transferred in bytes.
Transfer End by EDTCR Change from 1, 2, or 4 to 0
Transfer End by Transfer Size Error Interrupt
Ending EXDMA Transfer
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