R5F61668RD50FPV Renesas Electronics America, R5F61668RD50FPV Datasheet - Page 329
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R5F61668RD50FPV
Manufacturer Part Number
R5F61668RD50FPV
Description
MCU 3V 1024K I-TEMP 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668RN50FPV.pdf
(1506 pages)
Specifications of R5F61668RD50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61668RD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(2)
Even if the fast-page mode is selected, the DRAM space is not consecutively accessed and other
spaces may be accessed. The RAS signal can be held low during other space accesses. The fast-
page mode access can be resumed (burst access) when the same row address in the DRAM space
is accessed.
(a)
Set the RCDM and BE bits in DRAMCR to 1 to make a transition to the RAS down mode.
The RCDM bit is enabled only when the BE bit is set to 1.
The fast-page mode access (burst access) is resumed when the row addresses of the current cycle
and previous cycle are the same. While other spaces are accessed when the DRAM space access is
halted, the RAS signal must be low. Figure 9.50 shows a timing example of RAS down mode.
The RAS signal goes high under the following conditions.
• When a refresh cycle is performed during RAS down mode
• When a self-refresh is performed
• When a transition to software standby mode is made
• When the external bus requested by the BREQ signal is released
• When either the RCDM or BE bit is cleared to 0
If a transition to the all-module clock-stop mode is made during RAS down mode, clocks are
stopped with the RAS signal driven low. To make a transition with the RAS signal driven high,
clear the RCDM bit to 0 before execution of the SLEEP instruction.
Clear the RCDM bit to 0 for write access to SCKCR to set the clock frequencies. For SCKCR, see
section 27, Clock Pulse Generator.
RAS Down Mode and RAS Up Mode
RAS Down Mode
Rev. 2.00 Sep. 24, 2008 Page 295 of 1468
Section 9 Bus Controller (BSC)
REJ09B0412-0200
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