PI7C8154BNAIE Pericom Semiconductor, PI7C8154BNAIE Datasheet - Page 99

• Manufacturer Part Number: PI7C8154BNAIE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.63
14.1.64
14.1.65
14.1.66
CAPABILITY ID REGISTER – OFFSET E8h
NEXT POINTER REGISTER – OFFSET E8h
VPD REGISTER – OFFSET E8h
VPD DATA REGISTER – OFFSET ECh
Bit
21:20
22
23
31:24
Bit
7:0
Bit
15:8
Bit
17:16
23:18
30:24
31
Bit
31:0
Function
PI (Programming
Interface)
EXT (ENUM#
Status –
Extraction)
INS (ENUM#
Status –
Insertion)
Reserved
Function
Capability ID
Function
Next Pointer
Function
Reserved
VPD Address
Reserved
VPD Operation
Function
VPD Data
Type
R/O
R/WC
R/WC
R/O
Type
R/O
Type
R/O
Type
R/O
R/W
R/O
R/W
Type
R/W
Page 99 of 114
Description
Read as 01 to indicate in addition to the features of Programming
Interface 0, Device Hiding, the DHA bit and the PIE bit are implemented
0: ENUM# is not asserted
1: ENUM# is asserted
Reset to 0
0: ENUM# is not asserted
1: ENUM# is asserted
Reset to 0
Returns 0 when read. Reset to 0
Description
Read as 03h to indicate these are VPD registers
Description
E4: HS_EN is 1
00: HS_EN is 0
Description
Returns 0 when read. Reset to 0
VPD address for read / write cycle
Returns 0 when read. Reset to 0
Writing a 0 to this bit generates a read cycle from the EEPROM at the
VPD address specified in bits[7:2] of this register. This bit remains 0
until EEPROM cycle is finished, after which it will be set to 1. Data for
reads are available at offset ECh.
Writing a 1 to this bit generates a write cycle to the EEPROM at the VPD
address specified in bits[7:2] of this register. This bit remains at 1 until
EEPROM cycle is finished, after which it will be cleared to 0.
Reset to 0
Description
VPD data (EEPROM data [address + 0x40].
The least significant byte of this register corresponds to the byte of VPD
at the address specified by the VPD address register. The data from or
written to this register uses the normal PCI byte transfer capabilities.
Reset to 0
ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
PCI-to-PCI BRIDGE
Advance Information
PI7C8154B