PI7C8154BNAIE Pericom Semiconductor, PI7C8154BNAIE Datasheet - Page 59

• Manufacturer Part Number: PI7C8154BNAIE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note: x=don’t care
Table 5-3 shows setting data parity detected bit in the primary interface’s status register. This bit is
set under the following conditions:
Table 5-3 SETTING THE PRIMARY INTERFACE DATA PARITY DETECTED BIT (bit
24 of offset 04h)
Note: x=don’t care
Table 5-4 shows setting the data parity detected bit in the status register of secondary interface.
This bit is set under the following conditions:
Table 5-4 SETTING THE SECONDARY INTERFACE DATA PARITY DETECTED BIT
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
Detected Parity
Detected Parity
Primary Data
Detected Bit
Secondary
PI7C8154B must be a master on the primary bus.
The parity error response bit in the command register, corresponding to the primary interface,
must be set.
The P_PERR# signal is detected asserted or a parity error is detected on the primary bus.
The PI7C8154B must be a master on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary interface.
The S_PERR# signal is detected asserted or a parity error is detected on the secondary bus.
Secondary
Parity Bit
Error Bit
Transaction Type
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
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Direction
Direction
Direction
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Bus Where Error
Bus Where Error
Bus Where Error
Was Detected
Was Detected
Was Detected
ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
Primary/ Secondary Parity
Primary / Secondary Parity
Primary / Secondary Parity
Error Response Bits
Error Response Bits
Error Response Bits
PCI-to-PCI BRIDGE
Advance Information
x / x
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1 / x
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1 / x
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x / 1
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x / 1
PI7C8154B