PI7C8154BNAIE Pericom Semiconductor, PI7C8154BNAIE Datasheet - Page 56

• Manufacturer Part Number: PI7C8154BNAIE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

For downstream transactions, when PI7C8154B is delivering data to the target on the secondary
bus and S_PERR# is asserted by the target, the following events occur:
Similarly, for upstream transactions, when PI7C8154B is delivering data to the target on the
primary bus and P_PERR# is asserted by the target, the following events occur:
A delayed write transaction is completed on the initiator bus when the initiator repeats the write
transaction with the same address, command, data, and byte enable bits as the delayed write
command that is at the head of the posted data queue. Note that the parity bit is not compared when
determining whether the transaction matches those in the delayed transaction queues.
Two cases must be considered:
For downstream delayed write transactions, when the parity error is detected on the initiator bus
and PI7C8154B has write status to return, the following events occur:
Similarly, for upstream delayed write transactions, when the parity error is detected on the initiator
bus and PI7C8154B has write status to return, the following events occur:
For downstream transactions, where the parity error is being passed back from the target bus and
the parity error condition was not originally detected on the initiator bus, the following events
occur:
PI7C8154B sets the secondary interface data parity detected bit in the secondary status
register, if the secondary parity error response bit is set in the bridge control register.
PI7C8154B captures the parity error condition to forward it back to the initiator on the primary
bus.
PI7C8154B sets the primary interface data-parity-detected bit in the status register, if the
primary parity-error-response bit is set in the command register.
PI7C8154B captures the parity error condition to forward it back to the initiator on the
secondary bus.
When parity error is detected on the initiator bus on a subsequent re-attempt of the transaction
and was not detected on the target bus.
When parity error is forwarded back from the target bus
PI7C8154B first asserts P_TRDY# and then asserts P_PERR# two cycles later, if the primary
interface parity-error-response bit is set in the command register.
PI7C8154B sets the primary interface parity-error-detected bit in the status register.
Because there was not an exact data and parity match, the write status is not returned and the
transaction remains in the queue.
PI7C8154B first asserts S_TRDY# and then asserts S_PERR# two cycles later; if the
secondary interface parity-error-response bit is set in the bridge control register (offset 3Ch).
PI7C8154B sets the secondary interface parity-error-detected bit in the secondary status
register.
Because there was not an exact data and parity match, the write status is not returned and the
transaction remains in the queue.
Bridge asserts P_PERR# two cycles after the data transfer, if the following are both true:
The parity-error-response bit is set in the command register of the primary interface
The parity-error-response bit is set in the bridge control register of the secondary interface
Page 56 of 114
ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
PCI-to-PCI BRIDGE
Advance Information
PI7C8154B