PI7C8154BNAIE Pericom Semiconductor, PI7C8154BNAIE Datasheet - Page 97

• Manufacturer Part Number: PI7C8154BNAIE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.53
14.1.54
14.1.55
14.1.56
14.1.57
CHASSIS NUMBER REGISTER – OFFSET B0h
CAPABILITY ID REGISTER – OFFSET DCh
NEXT ITEM POINTER REGISTER – OFFSET DCh
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET DCh
POWER MANAGEMENT DATA REGISTER – OFFSET E0h
Bit
31:24
Bit
7:0
Bit
15:8
Bit
18:16
19
20
21
24:22
25
26
31:27
Bit
1:0
7:2
8
Function
Chassis Number
Function
Enhanced
Capabilities ID
Function
Next Item
Pointer
Function
Power
Management
Revision
PME# Clock
Auxiliary Power
Device Specific
Initialization
Reserved
D1 Power State
Support
D2 Power State
Support
PME# Support
Function
Power State
Reserved
PME_L Enable
Type
R/W
Type
R/O
Type
R/O
Type
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
Type
R/W
R/O
R/O
Page 97 of 114
Description
Indicates chassis number
Reset to 0
Description
Read as 01h to indicate that these are power management enhanced
capability registers.
Description
Read as B0h. Points to slot number register.
Description
Read as 001 to indicate the device is compliant to Revision 1.0 of PCI
Power Management Interface Specifications.
Read as 0 to indicate Bridge does not support the PME# pin.
Read as 0 to indicate bridge does not support the PME# pin or an
auxiliary power source.
Read as 0 to indicate bridge does not have device specific initialization
requirements.
Read as 0
Read as 0 to indicate bridge does not support the D1 power management
state.
Read as 0 to indicate bridge does not support the D2 power management
state.
Read as 0 to indicate bridge does not support the PME# pin.
Description
Indicates the current power state of bridge. If an unimplemented power
state is written to this register, bridge completes the write transaction,
ignores the write data, and does not change the value of the field. Writing
a value of D0 when the previous state was D3 cause a chip reset without
asserting S_RESET#
00: D0 state
01: D1 state (supported if bit[25] offset DCh is HIGH)
10: D2 state (supported if bit[26] offset DCh is HIGH)
11: D3 state
Reset to 0
Read as 0
Read as 0 as bridge does not support the PME# pin.
ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
PCI-to-PCI BRIDGE
Advance Information
PI7C8154B