PI7C8154BNAIE Pericom Semiconductor, PI7C8154BNAIE Datasheet - Page 14

• Manufacturer Part Number: PI7C8154BNAIE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.2.2
PRIMARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION
Name
P_M66EN
Name
P_AD[63:32]
P_CBE[7:4]
P_PAR64
Pin #
AB10
Pin #
AA16, AB16, AA17, AB17,
Y17, AB18, AC18, AA18,
AC19, AA19, AB20, Y19,
AA20, AB21, AC21, AA21,
Y20, AA23, Y21, W20,
Y23, W21, W23, W22, V21,
V23, V22, U23, U20, U22,
T23, T22
AA15, AB15, Y15, AC15
T21
Page 14 of 112
Type
Type
TS
TS
TS
I
Description
Primary Interface 66MHz Operation.
This input is used to specify if bridge is capable of
running at 66MHz. For 66MHz operation on the
Primary bus, this signal should be pulled “HIGH”.
For 33MHz operation on the Primary bus, this signal
should be pulled “LOW”. In this condition,
S_M66EN will be driven “LOW”, forcing the
secondary bus to run at 33MHz also.
Description
Primary Upper 32-bit Address / Data:
Multiplexed address and data bus providing an
additional 32 bits to the primary. When a dual
address command is used and P_REQ64# is
asserted, the initiator drives the upper 32 bits of the
64-bit address. Otherwise, these bits are undefined
and driven to valid logic levels. During the data
phase of a transaction, the initiator drives the upper
32 bits of the 64-bit write data, or the target drives
the upper 32 bits of the 64-bit read data, when
P_REQ64# and P_ACK64# are both asserted.
Otherwise, these bits are pulled up to a valid logic
level through external resistors.
Primary Upper 32-bit Command/Byte Enables:
Multiplexed command field and byte enable field.
During address phase, when the dual address
command is used and P_REQ64# is asserted, the
initiator drives the transaction type on these pins.
Otherwise, these bits are undefined, and the initiator
drives a valid logic level onto the pins. For read and
write transactions, the initiator drives these bits for
the P_AD[63:32] data bits when P_REQ64# and
P_ACK64# are both asserted. When not driven,
these bits are pulled up to a valid logic level through
external resistors.
Primary Upper 32-bit Parity: P_PAR64 carries
the even parity of P_AD[63:32] and P_CBE[7:4] for
both address and data phases. P_PAR64 is driven
by the initiator and is valid 1 cycle after the first
address phase when a dual address command is used
and P_REQ64# is asserted. P_PAR64 is valid 1
clock cycle after the second address phase of a dual
address transaction when P_REQ64# is asserted.
P_PAR64 is valid 1 cycle after valid data is driven
when both P_REQ64# and P_ACK64# are asserted
for that data phase. P_PAR64 is driven by the
device driving read or write data 1 cycle after the
P_AD lines are driven. P_PAR64 is tri-stated 1
cycle after the P_AD lines are tri-stated. Devices
receive data sample P_PAR64 as an input to check
for possible parity errors during 64-bit transactions.
When not driven, P_PAR64 is pulled up to a valid
logic level through external resistors.
ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
PCI-to-PCI BRIDGE
Advance Information
PI7C8154B