PI7C8154BNAIE Pericom Semiconductor, PI7C8154BNAIE Datasheet - Page 67

• Manufacturer Part Number: PI7C8154BNAIE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.2.3
7.2.4
8
SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER
The internal arbiter is disabled when the secondary bus central function control pin, S_CFN#, is
tied HIGH. An external arbiter must then be used.
When S_CFN# is tied HIGH, PI7C8154B reconfigures two pins to be external request and grant
pins. The S_GNT#[0] pin is reconfigured to be the external request pin because it’s an output. The
S_REQ#[0] pin is reconfigured to be the external grant pin because it’s an input. When an external
arbiter is used, PI7C8154B uses the S_GNT#[0] pin to request the secondary bus. When the
reconfigured S_REQ#[0] pin is asserted LOW after PI7C8154B has asserted S_GNT#[0],
PI7C8154B initiates a transaction on the secondary bus one cycle later. If grant is asserted and
PI7C8154B has not asserted the request, PI7C8154B parks AD, CBE and PAR pins by driving
them to valid logic levels.
The unused secondary bus grant outputs, S_GNT#[8:1] are driven HIGH. The unused secondary
bus request inputs, S_REQ#[8:1], should be pulled HIGH.
BUS PARKING
Bus parking refers to driving the AD[31:0], CBE[3:0], and PAR lines to a known value while the
bus is idle. In general, the device implementing the bus arbiter is responsible for parking the bus or
assigning another device to park the bus. A device parks the bus when the bus is idle, its bus grant
is asserted, and the device’s request is not asserted. The AD[31:0] and CBE[3:0] signals should be
driven first, with the PAR signal driven one cycle later. The AD[63:32] and CBE[7:4] are not
driven and need to be pulled up to a valid logic level through external resistors.
PI7C8154B parks the primary bus only when P_GNT# is asserted, P_REQ# is de-asserted, and the
primary PCI bus is idle. When P_GNT# is de-asserted, PI7C8154B 3-states the P_AD, P_CBE, and
P_PAR signals on the next PCI clock cycle. If PI7C8154B is parking the primary PCI bus and
wants to initiate a transaction on that bus, then PI7C8154B can start the transaction on the next PCI
clock cycle by asserting P_FRAME# if P_GNT# is still asserted.
If the internal secondary bus arbiter is enabled, the secondary bus is always parked at the last
master that used the PCI bus. That is, PI7C8154B keeps the secondary bus grant asserted to a
particular master until a new secondary bus request comes along. After reset, PI7C8154B parks the
secondary bus at itself until transactions start occurring on the secondary bus. Offset 48h, bit 1, can
be set to 1 to park the secondary bus at PI7C8154B. By default, offset 48h, bit 1, is set to 0. If the
internal arbiter is disabled, PI7C8154B parks the secondary bus only when the reconfigured grant
signal, S_REQ#[0], is asserted and the secondary bus is idle.
GENERAL PURPOSE I/O INTERFACE
The PI7C8154B implements a 4-pin general purpose I/O interface. During normal operation,
device specific configuration registers control the GPIO interface. The GPIO interface can be used
for the following functions:
During secondary interface reset, the GPIO interface can be used to shift in a 16-bit serial
stream that serves as a secondary bus clock disable mask.
Along with the GPIO[3] pin, a live insertion bit can be used to bring the PI7C8154B to a halt
through hardware, permitting live insertion of option cards behind the PI7C8154B.
Page 67 of 114
ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
PCI-to-PCI BRIDGE
Advance Information
PI7C8154B