PI7C8154BNAIE Pericom Semiconductor, PI7C8154BNAIE Datasheet - Page 51

• Manufacturer Part Number: PI7C8154BNAIE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.2
4.3
the original delayed read request; that is, a delayed read completion transaction proceeds from the
target bus to the initiator bus.
PI7C8154B does not combine or merge write transactions:
GENERAL ORDERING GUIDELINES
Independent transactions on primary and secondary buses have a relationship only when those
transactions cross PI7C8154B.
The following general ordering guidelines govern transactions crossing PI7C8154B:
ORDERING RULES
Table 4-1 shows the ordering relationships of all the transactions and refers by number to the
ordering rules that follow.
Table 4-1 SUMMARY OF TRANSACTION ORDERING
Pass
Posted Write
Delayed Read Request
PI7C8154B does not combine separate write transactions into a single write transaction—this
optimization is best implemented in the originating master.
PI7C8154B does not merge bytes on separate masked write transactions to the same DWORD
address—this optimization is also best implemented in the originating master.
PI7C8154B does not collapse sequential write transactions to the same address into a single
write transaction - the PCI Local Bus Specification does not permit this combining of
transactions.
The ordering relationship of a transaction with respect to other transactions is determined when
the transaction completes, that is, when a transaction ends with a termination other than target
retry.
Requests terminated with target retry can be accepted and completed in any order with respect
to other transactions that have been terminated with target retry. If the order of completion of
delayed requests is important, the initiator should not start a second delayed transaction until
the first one has been completed. If more than one delayed transaction is initiated, the initiator
should repeat all delayed transaction requests, using some fairness algorithm. Repeating a
delayed transaction cannot be contingent on completion of another delayed transaction.
Otherwise, a deadlock can occur.
Write transactions flowing in one direction have no ordering requirements with respect to write
transactions flowing in the other direction. PI7C8154B can accept posted write transactions on
both interfaces at the same time, as well as initiate posted write transactions on both interfaces
at the same time.
The acceptance of a posted memory write transaction as a target can never be contingent on the
completion of a non-locked, non-posted transaction as a master. This is true for PI7C8154B
and must also be true for other bus agents. Otherwise, a deadlock can occur.
PI7C8154B accepts posted write transactions, regardless of the state of completion of any
delayed transactions being forwarded across PI7C8154B.
Posted
Write
No
No
1
2
Page 51 of 114
Delayed Read
Request
Yes
No
5
Delayed Write
Request
Yes
No
5
Delayed Read
Completion
Yes
Yes
ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
5
PCI-to-PCI BRIDGE
Advance Information
Delayed Write
Completion
Yes
Yes
PI7C8154B
5