PI7C8154BNAIE Pericom Semiconductor, PI7C8154BNAIE Datasheet - Page 70

• Manufacturer Part Number: PI7C8154BNAIE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.3
9
9.1
After the shift operation is complete, the bridge tri-states the GPIO signals and deasserts
S_RESET#. PI7C8154B then ignores MSK_IN. Control of the GPIO signal now reverts to
PI7C8154B GPIO control registers. The clock disable mask can be modified subsequently through
a configuration write command to the secondary clock control register in device-specific
configuration space.
LIVE INSERTION
The GPIO[3] pin can be used, along with a live insertion mode bit, to disable transaction
forwarding.
To enable live insertion mode, the live insertion mode bit in the chip control register must be set to
1, and the output enable control for GPIO[3] must be set to input only in the GPIO output enable
control register. When live insertion mode is enabled, whenever GPIO[3] is driven to a value of 1,
the I/O enable, the memory enable, and the master enable bits are internally masked to 0. This
means that, as a target, PI7C8154B no longer accepts any I/O or memory transactions, on either
interface. When read, the register bits still reflect the value originally written by a configuration
write command; when GPIO[3] is deasserted, the internal enable bits return to their original value
(as they appear when read from the command register). When this mode is enabled, as a master,
PI7C8154B completes any posted write or delayed request transactions that have already been
queued.
Delayed completion transactions are not returned to the master in this mode because the bridge is
not responding to any I/O or memory transactions during this time. PI7C8154B continues to accept
Type 0 configuration transactions in live insertion mode. Once live insertion mode brings the
bridge to a halt and queued transactions are completed, the secondary reset bit in the bridge control
register can be used to assert S_RESET#, if desired, to reset and tri-state secondary bus devices,
and to enable any live insertion hardware.
EEPROM INTERFACE
The EEPROM interface consists of three pins: EECLK (EEPROM clock output), EEPD
(EEPROM bi-directional serial data), and EE_EN# (EEPROM enable on a LOW input). The
bridge may control an ISSI IS24C02 or compatible part, which is organized into 256x8 bits. The
EEPROM is used to initialize a select number of registers. This is accomplished after P_RESET#
is deasserted, at which time the data from the EEPROM will be loaded. The EEPROM interface is
organized into a 16-bit base, and the bridge supplies a 7-bit EEPROM word address. The bridge
does not control the EEPROM address input. It can only access the EEPROM with address input
set to 0.
AUTO MODE EEPROM ACCESS
The bridge may access the EEPROM in a WORD format by utilizing the auto mode through a
hardware sequencer. The EEPROM start control, address, and read/write commands can be
accessed through the configuration register. Before each access, the software should check the
Start EEPROM bit before issuing the next start.
Page 70 of 114
ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
PCI-to-PCI BRIDGE
Advance Information
PI7C8154B