PI7C8154BNAIE Pericom Semiconductor, PI7C8154BNAIE Datasheet - Page 55

• Manufacturer Part Number: PI7C8154BNAIE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.2.3
For upstream transactions, when PI7C8154B detects a read data parity error on the primary bus, the
following events occur:
PI7C8154B returns to the initiator the data and parity that was received from the target. When the
initiator detects a parity error on this read data and is enabled to report it, the initiator asserts
PERR# two cycles after the data transfer occurs. It is assumed that the initiator takes responsibility
for handling a parity error condition; therefore, when PI7C8154B detects PERR# asserted while
returning read data to the initiator, PI7C8154B does not take any further action and completes the
transaction normally.
DELAYED WRITE TRANSACTIONS
When PI7C8154B detects a data parity error during a delayed write transaction, the initiator drives
data and data parity, and the target checks parity and conditionally asserts PERR#.
For delayed write transactions, a parity error can occur at the following times:
When a delayed write transaction is normally queued, the address, command, address parity, data,
byte enable bits, and data parity are all captured and a target retry is returned to the initiator. When
PI7C8154B detects a parity error on the write data for the initial delayed write request transaction,
the following events occur:
Note: If parity checking is turned off and data parity errors have occurred for queued or subsequent
delayed write transactions on the initiator bus, it is possible that the initiator’s re-attempts of the
write transaction may not match the original queued delayed write information contained in the
delayed transaction queue. In this case, a master timeout condition may occur, possibly resulting in
a system error (P_SERR# assertion).
PI7C8154B asserts P_PERR# 2 cycles following the data transfer, if the primary interface
parity error response bit is set in the command register.
PI7C8154B sets the detected parity error bit in the primary status register.
PI7C8154B sets the data parity detected bit in the primary status register, if the primary
interface parity-error-response bit is set in the command register.
PI7C8154B forwards the bad parity with the data back to the initiator on the secondary bus. If
the data with the bad parity is pre-fetched and is not read by the initiator on the secondary bus,
the data is discarded and the data with bad parity is not returned to the initiator.
PI7C8154B completes the transaction normally.
During the original delayed write request transaction
When the initiator repeats the delayed write request transaction
When PI7C8154B completes the delayed write transaction to the target
If the parity-error-response bit corresponding to the initiator bus is set, PI7C8154B asserts
TRDY# to the initiator and the transaction is not queued. If multiple data phases are requested,
STOP# is also asserted to cause a target disconnect. Two cycles after the data transfer,
PI7C8154B also asserts PERR#.
If the parity-error-response bit is not set, PI7C8154B returns a target retry. It queues the
transaction as usual. PI7C8154B does not assert PERR#. In this case, the initiator repeats the
transaction.
PI7C8154B sets the detected-parity-error bit in the status register corresponding to the initiator
bus, regardless of the state of the parity-error-response bit.
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ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
PCI-to-PCI BRIDGE
Advance Information
PI7C8154B