PI7C8154BNAIE Pericom Semiconductor, PI7C8154BNAIE Datasheet - Page 81

• Manufacturer Part Number: PI7C8154BNAIE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.16
14.1.17
I/O LIMIT REGISTER – OFFSET 1Ch
SECONDARY STATUS REGISTER – OFFSET 1Ch
Bit
7:4
Bit
9:8
11:10
15:12
Bit
20:16
21
22
23
24
26:25
27
28
29
30
Function
I/O Base Address
[15:12]
Function
32-bit Indicator
Reserved
I/O Limit
Address
[15:12]
Function
Reserved
66MHz Capable
Reserved
Fast Back-to-
Back Capable
Data Parity Error
Detected
DEVSEL#
timing
Signaled Target
Abort
Received Target
Abort
Received Master
Abort
Received System
Error
Type
R/W
Type
R/O
R/O
R/W
Type
R/O
R/O
R/O
R/O
R/WC
R/O
R/WC
R/WC
R/WC
R/WC
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Description
Defines the bottom address of the I/O address range for the bridge to
determine when to forward I/O transactions from one interface to the
other. The upper 4 bits correspond to address bits [15:12] and are
writable. The lower 12 bits corresponding to address bits [11:0] are
assumed to be 0. The upper 16 bits corresponding to address bits [31:16]
are defined in the I/O base address upper 16 bits address register
Reset to 0
Description
Read as 01h to indicate 32-bit I/O addressing
Returns 00 when read. Reset to 00
Defines the top address of the I/O address range for the bridge to
determine when to forward I/O transactions from one interface to the
other. The upper 4 bits correspond to address bits [15:12] and are
writable. The lower 12 bits corresponding to address bits [11:0] are
assumed to be FFFh. The upper 16 bits corresponding to address bits
[31:16] are defined in the I/O limit address upper 16 bits address register
Reset to 0
Description
Reset to 0
Set to 1 to enable 66MHz operation on the secondary interface
Reset to 1
Reset to 0
Set to 1 to indicate bridge is capable of decoding fast back-to-back
transactions on the secondary interface to different targets
Reset to 1
Set to 1 when S_PERR# is asserted and bit 6 of command register is set
Reset to 0
DEVSEL# timing (medium decoding)
01: medium DEVSEL# decoding
Reset to 01
Set to 1 (by a target device) whenever a target abort cycle occurs on its
secondary interface
Reset to 0
Set to 1 (by a master device) whenever transactions on its secondary
interface are terminated with target abort
Reset to 0
Set to 1 (by a master) when transactions on its secondary interface are
terminated with Master Abort
Reset to 0
Set to 1 when S_SERR# is asserted
Reset to 0
ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
PCI-to-PCI BRIDGE
Advance Information
PI7C8154B