PI7C8154BNAIE Pericom Semiconductor, PI7C8154BNAIE Datasheet - Page 58

• Manufacturer Part Number: PI7C8154BNAIE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.3
Assertion of P_SERR# is used to signal the parity error condition when the initiator does not know
that the error occurred. Because the data has already been delivered with no errors, there is no other
way to signal this information back to the initiator. If the parity error has forwarded from the
initiating bus to the target bus, P_SERR# will not be asserted.
DATA PARITY ERROR REPORTING
In the previous sections, the responses of the bridge to data parity errors are presented according to
the type of transaction in progress. This section organizes the responses of the bridge to data parity
errors according to the status bits that the bridge sets and the signals that it asserts.
Table 5-1 shows setting the detected parity error bit in the status register, corresponding to the
primary interface. This bit is set when PI7C8154B detects a parity error on the primary interface.
Table 5-1 SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR BIT
(bit 31 of offset 04h)
Note: x=don’t care
Table 5-2 shows setting the detected parity error bit in the secondary status register, corresponding
to the secondary interface. This bit is set when PI7C8154B detects a parity error on the secondary
interface.
Table 5-2 SETTING THE SECONDARY INTERFACE DETECTED PARITY ERROR BIT
Primary Detected
0
0
1
0
1
0
0
0
1
0
0
0
0
1
Parity Error Bit
Detected Parity
Bridge sets the data parity detected bit in the status register, if the parity error response bit is
set in the command register of the primary interface.
Bridge asserts P_SERR# and sets the signaled system error bit in the status register, if all the
following conditions are met:
Secondary
Error Bit
The SERR# enable bit is set in the command register
The parity error response bit is set in the bridge control register of the secondary interface
The parity error response bit is set in the command register of the primary interface
Bridge has not detected the parity error on the secondary (initiator) bus, which the parity
error is not forwarded from the secondary bus to the primary bus
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Page 58 of 114
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Direction
Direction
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Bus Where Error
Bus Where Error
Was Detected
Was Detected
ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
Primary/ Secondary Parity
Primary/ Secondary Parity
Error Response Bits
Error Response Bits
PCI-to-PCI BRIDGE
Advance Information
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
PI7C8154B