PI7C8154BNAIE Pericom Semiconductor, PI7C8154BNAIE Datasheet - Page 102

• Manufacturer Part Number: PI7C8154BNAIE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.1.1
16.1.2
describe the boundary-scan test logic elements: TAP pins, instruction register, test data registers
and TAP controller. Figure 16-1 illustrates how these pieces fit together to form the JTAG unit.
Figure 16-1 TEST ACCESS PORT DIAGRAM
TAP PINS
The PI7C8154B’s TAP pins form a serial port composed of four input connections (TMS, TCK,
TRST# and TDI) and one output connection (TDO). These pins are described in Table 16-1. The
TAP pins provide access to the instruction register and the test data registers.
INSTRUCTION REGISTER
The Instruction Register (IR) holds instruction codes. These codes are shifted in through the Test
Data Input (TDI) pin. The instruction codes are used to select the specific test operation to be
performed and the test data register to be accessed.
The instruction register is a parallel-loadable, master/slave-configured 5-bit wide, serial-shift
register with latched outputs. Data is shifted into and out of the IR serially through the TDI pin
clocked by the rising edge of TCK. The shifted-in instruction becomes active upon latching from
the master stage to the slave stage. At that time the IR outputs along with the TAP finite state
machine outputs are decoded to select and control the test data register selected by that instruction.
Upon latching, all actions caused by any previous instructions terminate.
The instruction determines the test to be performed, the test data register to be accessed, or both.
The IR is two bits wide. When the IR is selected, the most significant bit is connected to TDI, and
the least significant bit is connected to TDO. The value presented on the TDI pin is shifted into the
IR on each rising edge of TCK. The TAP controller captures fixed parallel data (1101 binary).
When a new instruction is shifted in through TDI, the value 1101(binary) is always shifted out
through TDO, least significant bit first. This helps identify instructions in a long chain of serial data
from several devices.
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ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
PCI-to-PCI BRIDGE
Advance Information
PI7C8154B