PI7C8154BNAIE Pericom Semiconductor, PI7C8154BNAIE Datasheet - Page 36

• Manufacturer Part Number: PI7C8154BNAIE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.9.3
2.9.4
64-BIT TRANSACTIONS – DATA PHASE
PI7C8154B asserts REQ64# to indicate it is initiating a 64-bit transfer during memory write
transactions. During the data phase, PI7C8154B asserts the following:
Every data phase will consist of 64 bits and 8 byte enable bits when PI7C8154B detects ACK64##
asserted by the target at the same time it detects DEVSEL#.
For write transactions, PI7C8154B redirects the write data that it has on the AD[63:32] bus to
AD[31:0] during the second data phase if it does not detect ACK64# asserted at the same time that
it detects DEVSEL# asserted. Also, the CBE[7:4] is redirected to CBE[3:0] during the second data
phase.
For 64-bit memory write transactions that end at an odd DWORD boundary, PI7C8154B drives the
byte enable bits to 1 during the last data phase. AD[63:32] are then unpredictable but are driven to
a valid logic level.
For read transactions, PI7C8154B drives 8 bits of byte enables on CBE[7:0] when it has asserted
REQ64#. CBE[7:0] is always 0 because the only read transactions that use the 64-bit extension are
prefetchable memory reads. No special redirection is needed based on the target’s assertion or lack
of assertion of ACK64#. When the target asserts ACK64# at the same time that it asserts
DEVSEL#, all read data transfers consist of 64 bits and the target asserts PAR64, which covers
AD[63:32] and CBE[7:4]. All data phase consist of 32-bit transactions when the target does not
assert ACK64# and asserts DEVSEL#.
64-BIT TRANSACTIONS – RECEIVED BY PI7C8154B
PI7C8154B does one of 2 things when it is the target of a transaction and REQ64# is asserted.
PI7C8154B either asserts ACK64# at the same time it asserts DEVSEL# to indicate its ability to
perform 64-bit data transfers, or it does not use the 64-bit extension as a target and does not assert
ACK64#. PI7C8154B does not assert ACK64# under any of the following conditions:
If PI7C8154B is the target of a 64-bit memory write transaction, it is able to accept 64 bits of data
during each data phase. If PI7C8154B is the target of a memory read transaction, it delivers 64 bits
of read data during each data phase and drives PAR64 corresponding to AD[63:32] and CBE[7:4]
for each data phase. If an odd number of DWORDS is read from the target and PI7C8154B has
asserted ACK64# when returning read data to the initiator, PI7C8154B disconnects before the last
DWORD is returned. PI7C8154B may have read an odd number of DWORD’s because of either a
The low 32 bits of data on AD[31:0]
The low 4 bits on CBE[3:0]
The high 32 bits of data on AD[63:32]
The high 4 bits on CBE[7:4]
REQ64# was not asserted by the initiator
PI7C8154B is responding to a non-prefetchable memory read transaction
PI7C8154B is responding to an I/O transaction
PI7C8154B is responding to a configuration transaction
Only 1 DWORD of data was read from the target
Page 36 of 112
ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
PCI-to-PCI BRIDGE
Advance Information
PI7C8154B