PI7C8154BNAIE Pericom Semiconductor, PI7C8154BNAIE Datasheet - Page 44

• Manufacturer Part Number: PI7C8154BNAIE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.1
3.2
ADDRESS RANGES
PI7C8154B uses the following address ranges that determine which I/O and memory transactions
are forwarded from the primary PCI bus to the secondary PCI bus, and from the secondary bus to
the primary bus:
Transactions falling within these ranges are forwarded downstream from the primary PCI bus to the
secondary PCI bus. Transactions falling outside these ranges are forwarded upstream from the
secondary PCI bus to the primary PCI bus.
No address translation is required in PI7C8154B. The addresses that are not marked for
downstream are always forwarded upstream.
I/O ADDRESS DECODING
PI7C8154B uses the following mechanisms that are defined in the configuration space to specify
the I/O address space for downstream and upstream forwarding:
This section provides information on the I/O address registers and ISA mode Section 3.4 provides
information on the VGA modes.
To enable downstream forwarding of I/O transactions, the I/O enable bit must be set in the
command register in configuration space. All I/O transactions initiated on the primary bus will be
ignored if the I/O enable bit is not set. To enable upstream forwarding of I/O transactions, the
master enable bit must be set in the command register. If the master-enable bit is not set,
PI7C8154B ignores all I/O and memory transactions initiated on the secondary bus.
The master-enable bit also allows upstream forwarding of memory transactions if it is set.
CAUTION
If any configuration state affecting I/O transaction forwarding is changed by a configuration write
operation on the primary bus at the same time that I/O transactions are ongoing on the secondary
bus, PI7C8154B response to the secondary bus I/O transactions is not predictable. Configure the
I/O base and limit address registers, ISA enable bit, VGA mode bit, and VGA snoop bit before
setting I/O enable and master enable bits, and change them subsequently only when the primary
and secondary PCI buses are idle.
Two 32-bit I/O address ranges
Two 32-bit memory-mapped I/O (non-prefetchable memory) ranges
Two 32-bit prefetchable memory address ranges
I/O base and limit address registers
The ISA enable bit
The VGA mode bit
The VGA snoop bit
Page 44 of 114
ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
PCI-to-PCI BRIDGE
Advance Information
PI7C8154B