PI7C8154BNAIE Pericom Semiconductor, PI7C8154BNAIE Datasheet - Page 110

• Manufacturer Part Number: PI7C8154BNAIE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.4
17.5
17.6
1. See Figure 17-1 PCI Signal Timing Measurement Conditions.
2. All primary interface signals are synchronized to P_CLK. All secondary interface signals are
3. Point-to-point signals are P_REQ#, S_REQ#[7:0], P_GNT#, S_GNT#[7:0], HSLED, HS_SW#,
4. REQ# signals have a setup of 10ns and GNT# signals have a setup of 12ns.
66MHZ PCI SIGNALING TIMING
33MHZ PCI SIGNALING TIMING
RESET TIMING
Symbol
Tsu
Tsu(ptp)
Th
Tval
Tval(ptp)
Ton
Toff
Symbol
T
T
T
T
T
Symbol
T
T
T
T
T
Symbol
T
T
T
T
T
T
synchronized to S_CLKOUT.
HS_EN, and ENUM#. Bused signals are P_AD, P_BDE#, P_PAR, P_PERR#, P_SERR#,
P_FRAME#, P_IRDY#, P_TRDY#, P_LOCK#, P_DEVSEL#, P_STOP#, P_IDSEL, P_PAR64,
P_REQ64#, P_ACK64#, S_AD, S_CBE#, S_PAR, S_PERR#, S_SERR#, S_FRAME#,
S_IRDY#, S_TRDY#, S_LOCK#, S_DEVSEL#, S_STOP#, S_PA64, S_REQ64#, and
S_ACK64#.
SKEW
DELAY
CYCLE
HIGH
LOW
SKEW
DELAY
CYCLE
HIGH
LOW
RST
RST-CLK
RST-OFF
SRST
SRST-ON
DRST
Parameter
SKEW among S_CLKOUT[9:0]
DELAY between PCLK and S_CLKOUT[9:0]
P_CLK, S_CLKOUT[9:0] cycle time
P_CLK, S_CLKOUT[9:0] HIGH time
P_CLK, S_CLKOUT[9:0] LOW time
Parameter
SKEW among S_CLKOUT[9:0]
DELAY between PCLK and S_CLKOUT[9:0]
P_CLK, S_CLKOUT[9:0] cycle time
P_CLK, S_CLKOUT[9:0] HIGH time
P_CLK, S_CLKOUT[9:0] LOW time
Parameter
P_RESET# active time after power stable
P_RESET# active time after P_CLK stable
P_RESET# active-to-output float delay
S_RESET# active after P_RESET# assertion
S_RESET# active time after S_CLKIN stable
S_RESET# deassertion after P_RESET# deassertion
Parameter
Input setup time to CLK – bused signals
Input setup time to CLK – point-to-point
Input signal hold time from CLK
CLK to signal valid delay – bused signals
CLK to signal valid delay – point-to-point
Float to active delay
Active to float delay
1,2
1,2
Page 110 of 114
1,2
1,2,3
1,2,3
1,2,3
1,2,3
Condition
20pF load
Condition
20pF load
Min.
3
5
0
2
2
2
-
66 MHz
Max.
-
-
-
6
6
-
14
ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
Min.
Min.
Min.
3.47
3.47
100
100
Min.
7
10, 12
0
2
2
2
-
15
30
11
11
20
0
6
6
0
1
-
-
PCI-to-PCI BRIDGE
Advance Information
33 MHz
4
Max.
Max.
Max.
0.250
0.250
4.20
4.20
30
40
40
25
Max
.
-
-
-
11
12
-
28
-
-
-
PI7C8154B
Units
Units
Units
Units
cycles
ns
ns
ns
us
us
ns
ns
us