PI7C8154BNAIE Pericom Semiconductor, PI7C8154BNAIE Datasheet - Page 86

• Manufacturer Part Number: PI7C8154BNAIE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.30
14.1.31
DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h
ARBITER CONTROL REGISTER – OFFSET 40h
Bit
31-28
Bit
0
1
3:2
4
5
7:6
8
15:9
Bit
24:16
25
Function
Reserved
Function
Reserved
Memory Write
Disconnect
Control
Reserved
Secondary Bus
Prefetch Disable
Live Insertion
Mode
Reserved
Chip Reset
Reserved
Function
Arbiter Control
Priority of
Secondary
Interface
Type
R/O
Type
R/O
R/W
R/O
R/W
R/W
R/O
R/WR
R/O
Type
R/W
R/W
Page 86 of 114
Description
Reserved. Returns 0 when read. Reset to 0.
Description
Reserved. Returns 0 when read. Reset to 0
Controls when the bridge (as a target) disconnects memory write
transactions.
0: memory write disconnects at 4KB aligned address boundary
1: memory write disconnects at cache line aligned address boundary
Reset to 0
Reserved. Returns 0 when read. Reset to 0.
Controls the bridge’s ability to prefetch during upstream memory read
transactions
0: Bridge prefetches and does not forward byte enable bits during
upstream memory read transactions.
1: Bridge requests only 1 DWORD from the target and forwards read
byte enable bits during upstream memory reads.
Reset to 0
Enables control of transaction forwarding
0: GPIO[3] has no effect on the I/O, memory, and master enable bits
1: If GPIO[3] is set to input only, this bit enables GPIO[3] to mask the
I/O enable, memory enable, and master enable bits to 0. These bits are
masked when GPIO[3] is driven HIGH. As a result, PI7C8154 stops
accepting I/O and memory transactions.
Reset to 0
Reserved. Returns 0 when read. Reset to 0
Controls the chip and secondary bus reset.
0: Bridge is ready for operation
1: Causes Bridge to perform a chip reset
Reserved. Returns 0 when read. Reset to 0.
Description
Each bit controls whether a secondary bus master is assigned to the high
priority group or the low priority group.
Bits [24:16] correspond to request inputs S_REQ[8:0]
0: low priority
1: high priority
Reset to 0
Controls whether the secondary interface of the bridge is in the high
priority group or the low priority group.
0: low priority
1: high priority
Reset to 1
ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
PCI-to-PCI BRIDGE
Advance Information
PI7C8154B