PI7C8154BNAIE Pericom Semiconductor, PI7C8154BNAIE Datasheet
PI7C8154BNAIE
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PI7C8154B Asynchronous 2-Port PCI-to-PCI Bridge st 3545 North 1 Street, San Jose, CA 95134 Telephone: 1-877-PERICOM, (1-877-737-4266) Email: Internet: http://www.pericom.com REVISION 1.1 Fax: 408-435-1100 solutions@pericom.com ...
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... A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product ...
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REVISION HISTORY Date Revision Number 07/10/04 0.03 07/26/04 1.1 Description Initial release of preliminary specification Initial release of specification to the web Updated Power Dissipation in section 17.9 Updated T in sections 17.4 and 17.5 DELAY Revised V parameter in ...
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This page intentionally left blank. ASYNCHRONOUS 2-PORT Page 4 of 112 JUNE 2008 REVISION 1.1 PI7C8154B PCI-to-PCI BRIDGE Advance Information ...
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TABLE OF CONTENTS LIST OF TABLES...............................................................................................................................................10 LIST OF FIGURES.............................................................................................................................................10 INTRODUCTION ...............................................................................................................................................11 1 SIGNAL DEFINITIONS ...........................................................................................................................12 1.1 SIGNAL TYPES ................................................................................................................................12 1.2 SIGNALS ...........................................................................................................................................12 1.2.1 PRIMARY BUS INTERFACE SIGNALS ........................................................................................12 1.2.2 PRIMARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION ...................................................14 1.2.3 SECONDARY BUS ...
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TRANSACTION FLOW THROUGH ...............................................................................................37 2.11 TRANSACTION TERMINATION....................................................................................................37 2.11.1 MASTER TERMINATION INITIATED BY PI7C8154B............................................................38 2.11.2 MASTER ABORT RECEIVED BY PI7C8154B .........................................................................38 2.11.3 TARGET TERMINATION RECEIVED BY PI7C8154B............................................................39 2.11.3.1 DELAYED WRITE TARGET TERMINATION RESPONSE ......................................................39 2.11.3.2 POSTED WRITE TARGET TERMINATION RESPONSE.........................................................41 ...
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SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER .......................................67 7.2.4 BUS PARKING ..............................................................................................................................67 8 GENERAL PURPOSE I/O INTERFACE ...............................................................................................67 8.1 GPIO CONTROL REGISTERS.........................................................................................................68 8.2 SECONDARY CLOCK CONTROL..................................................................................................68 8.3 LIVE INSERTION .............................................................................................................................70 9 EEPROM INTERFACE............................................................................................................................70 9.1 AUTO MODE EEPROM ACCESS ...................................................................................................70 ...
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CAPABILITY POINTER REGISTER – OFFSET 34h ...............................................................84 14.1.27 INTERRUPT LINE REGISTER – OFFSET 3Ch .......................................................................84 14.1.28 INTERRUPT PIN REGISTER – OFFSET 3Ch .........................................................................84 14.1.29 BRIDGE CONTROL REGISTER – OFFSET 3Ch ....................................................................84 14.1.30 DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET ...
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TAP PINS ................................................................................................................................102 16.1.2 INSTRUCTION REGISTER ....................................................................................................102 16.2 BOUNDARY SCAN INSTRUCTION SET ....................................................................................103 16.3 TAP TEST DATA REGISTERS......................................................................................................103 16.4 BYPASS REGISTER .......................................................................................................................104 16.5 BOUNDARY SCAN REGISTER ....................................................................................................104 16.6 TAP CONTROLLER .......................................................................................................................104 17 ELECTRICAL AND TIMING SPECIFICATIONS.............................................................................109 17.1 MAXIMUM RATINGS ...
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LIST OF TABLES T 2-1 PCI TRANSACTIONS.......................................................................................................................23 ABLE T 2-2 WRITE TRANSACTION FORWARDING.......................................................................................25 ABLE T 2-3 WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES ............................................27 ABLE T 2-4 READ PREFETCH ADDRESS BOUNDARIES ...............................................................................29 ABLE T 2-5 READ TRANSACTION PREFETCHING.........................................................................................29 ABLE T 2-6 DEVICE ...
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... INTRODUCTION Product Description The PI7C8154B is Pericom Semiconductor’s PCI-to-PCI Bridge, designed to be fully compliant with the 64-bit, 66MHz implementation of the PCI Local Bus Specification, Revision 2.2. The PI7C8154B supports synchronous and asynchronous bus transactions between devices on the Primary Bus and the Secondary Buses operating up to 66MHz. For the PI7C8154B-80, the Secondary Bus supports up to 80MHz operation ...
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SIGNAL DEFINITIONS 1.1 SIGNAL TYPES Signal Type Description I Input Only O Output Only P Power TS Tri-State bi-directional STS Sustained Tri-State. Active LOW signal must be pulled HIGH for 1 cycle when deasserting. OD Open Drain 1.2 SIGNALS ...
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Name Pin # P_IRDY# AC5 P_TRDY# AB5 P_DEVSEL# AA6 P_STOP# AC6 P_LOCK# AB6 P_IDSEL Y1 P_PERR# AC7 P_SERR# Y7 P_REQ# U3 P_GNT# R2 P_RESET# R3 Page 13 of 112 ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE Advance Information Type Description STS Primary IRDY ...
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Name Pin # P_M66EN AB10 1.2.2 PRIMARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION Name Pin # P_AD[63:32] AA16, AB16, AA17, AB17, Y17, AB18, AC18, AA18, AC19, AA19, AB20, Y19, AA20, AB21, AC21, AA21, Y20, AA23, Y21, W20, Y23, W21, W23, ...
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Name Pin # P_REQ64# AC14 P_ACK64# AB14 1.2.3 SECONDARY BUS INTERFACE SIGNALS Name Pin # S_AD[31:0] C3, A3, B3, C4, A4, B4, C5, B5, A6, A7, D7, B7, A8, B8, C8, A9, C13, B13, A13, D13, C14, B14, C15, B15, ...
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Name Pin # S_TRDY# A10 S_DEVSEL# B10 S_STOP# C10 S_LOCK# A11 S_PERR# C11 S_SERR# B11 S_REQ#[8:0] E1, E3, D2, D1, E4, D3, C2, C1, D4 S_GNT#[8:0] H1, G3, G2, G4, G1, F2, F1, F3, E2 S_RESET# H2 S_M66EN A14 S_CFN# ...
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SECONDARY BUS INTERFACE SIGNALS – 64-EXTENSTION Name Pin # S_AD[63:32] C20, A21, D20, C21, C23, C22, D21, E20, D22, E21, E23, F21, F23, F22, G20, G22, G21, H23, H22, H21, J23, J20, J22, K23, K22, K21, L23, L21, L22, ...
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Name Pin # S_CLKIN J4 S_CLKOUT[9:0] P1, P2, P3, N1, N3, M2, M1, M3, L3, L2 ASYNC_SEL# AB1 ASYNC_CLKIN AB2 1.2.6 MISCELLANEOUS SIGNALS Name Pin # MSK_IN R21 P_VIO R20 S_VIO N22 BPCCE R4 ASYNCHRONOUS 2-PORT Type Description I Secondary ...
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CONFIG66 R22 PMEENA# D11 EEDATA A22 EECLK A23 EE_EN# AC22 NO CONNECT B6, AA22 1.2.7 GENERAL PURPOSE I/O INTERFACE SIGNALS Name Pin # GPIO[3:0] K2, K3, L4, L1 1.2.8 JTAG BOUNDARY SCAN SIGNALS Name Pin # TCK N20 TMS P21 ...
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Name Pin # VSS A1, A5, A12, A16, B2, B21, B22, C7, D8, D12, D16, D23, F4, F20, G23, H3, J2, K4, K20, L20, N2, P4, P20, T2, U21, V4, V20, Y8, Y9, Y12, Y16, AA2, AB22, AC1, AC4, AC13, ...
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BALL PIN NAME TYPE LOCATION E1 S_REQ#[8] E3 S_REQ#[ E21 S_AD[54] E23 S_AD[53] F1 S_GNT#[2] F3 S_GNT#[ F21 S_AD[52] F23 S_AD[51] G1 S_GNT#[4] G3 S_GNT#[ G21 S_AD[47] G23 VSS H1 S_GNT#[8] H3 VSS - ...
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BALL PIN NAME LOCATION - - U21 VSS U23 P_AD[36] V1 P_AD[27] V3 P_AD[26 V21 P_AD[39] V23 P_AD[38] W1 P_AD[24] W3 VDD - - W21 P_AD[42] W23 P_AD[41] Y1 P_IDSEL Y3 P_AD[22] Y5 P_AD[16] Y7 P_SERR# Y9 VSS ...
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BALL PIN NAME LOCATION AC19 P_AD[55] AC21 P_AD[49] AC23 VSS 2 SIGNAL DEFINITIONS This Chapter offers information about PCI transactions, transaction forwarding across PI7C8154B, and transaction termination. The PI7C8154B has two 128-byte buffers for read data buffering of upstream and ...
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PCI buses, either upstream or downstream, Type 1 configuration write must be used. PI7C8154B neither generates Type 0 configuration transactions on the primary PCI bus nor responds to Type 0 configuration transactions on the secondary ...
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Depending on the command type, PI7C8154B can support multiple data phase PCI transactions. For detailed descriptions of how PI7C8154B imposes disconnect boundaries, see Section 2.6.4 for write address boundaries and Section 2.7.3 read address boundaries. 2.6 WRITE TRANSACTIONS Write transactions ...
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PI7C8154B ends the transaction on the target bus when one of the following conditions is met: All posted write data has been delivered to the target. The target returns a target disconnect or target retry (PI7C8154B starts another transaction to ...
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PI7C8154B claims the access by asserting DEVSEL# and returns TRDY# to the initiator, to indicate that the write data was transferred. If the initiator requests multiple DWORD, PI7C8154B also asserts STOP# in conjunction with TRDY# to signal a target disconnect. ...
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Delayed write transactions are accepted as long as at least one open entry in the delayed transaction queue exists. Therefore, several posted and delayed write transactions can exist in data buffers at the same time. See Chapter 4 for information ...
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If extra read transactions could have side effects, for example, when accessing a FIFO, use non- prefetchable read transactions to those locations. Accordingly important to retain the value of the byte enable bits during the data phase, ...
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PI7C8154B accepts a delayed read request, by sampling the read address, read bus command, and ...
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When the master repeats the transaction and starts transferring prefetchable read data from data buffers while the read transaction on the target bus is still in progress and before a read boundary is reached on the target bus, the read ...
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Type 1 configuration transactions are issued when the intended target resides on another PCI bus, or when a special cycle generated on another PCI bus. A Type 1 configuration command is identified by the configuration command and ...
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The lowest two address bits on P_AD[1:0] are 01b. The bus number in address field P_AD[23:16] is equal to the value in the secondary bus number register in configuration space. The bus command on P_CBE[3: configuration read or ...
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TYPE 1 TO TYPE 1 FORWARDING Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism when two or more levels of PCI-to-PCI bridges are used. When PI7C8154B detects a Type 1 configuration transaction intended for a ...
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The data phase contains the special cycle message. The transaction is forwarded as a delayed transaction, but in this case the target response is not forwarded back ...
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TRANSACTIONS – DATA PHASE PI7C8154B asserts REQ64# to indicate it is initiating a 64-bit transfer during memory write transactions. During the data phase, PI7C8154B asserts the following: The low 32 bits of data on AD[31:0] The low 4 ...
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TRANSACTIONS – SUPPORT DURING RESET PI7C8154B checks P_REQ64# while P_RESET# is asserted to determine whether the 64-bit extensions are connected. If P_REQ64# ...
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FRAME# deasserts. If FRAME# is already deasserted, IRDY# can be deasserted on the next clock cycle following detection of the master abort condition. The target can terminate transactions with one of the following types of ...
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This sets the received-master-abort bit in the status register corresponding to the target bus. For delayed read and write transactions, PI7C8154B is able to reflect the master abort condition back to the initiator. When PI7C8154B ...
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Table 2-7 shows the response to each type of target termination that occurs during a delayed write transaction. PI7C8154B repeats a delayed write transaction until one of the following conditions is met: PI7C8154B completes at least one data transfer. PI7C8154B ...
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Table 2-7 DELAYED WRITE TARGET TERMINATION RESPONSE Target Termination Normal Target Retry Target Disconnect Target Abort After the PI7C8154B makes 2 target bus, PI7C8154B asserts P_SERR# if the SERR# enable bit (bit 8 of command register for the secondary bus) ...
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PI7C8154B repeats a delayed read transaction until one of the following conditions is met: PI7C8154B completes at least one data transfer. PI7C8154B receives ...
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FOR DELAYED READ TRANSACTIONS: The transaction is being entered into the delayed transaction queue. The read request has already been queued, but read data is not yet available. Data has been read from target, but it is not yet at ...
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ADDRESS RANGES PI7C8154B uses the following address ranges that determine which I/O and memory transactions are forwarded from the primary PCI bus to the secondary PCI bus, and from the secondary bus to the primary bus: Two 32-bit I/O ...
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I/O BASE AND LIMIT ADDRESS REGISTER PI7C8154B implements one set of I/O base and limit address registers in configuration space that define an I/O address range per port downstream forwarding. PI7C8154B supports 32-bit I/O addressing, which allows I/O addresses ...
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Accordingly, if the ISA enable bit is set, PI7C8154B forwards upstream those I/O transactions addressing the top 768 bytes of each aligned 1KB block within the first 64KB of I/O space. The master enable bit in the command configuration register ...
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The memory-mapped I/O range supports 32-bit addressing only. The PCI-to-PCI Bridge Architecture Specification does not provide for 64-bit addressing in the memory-mapped I/O space. The memory-mapped I/O address range has a granularity and alignment of 1MB. The maximum memory-mapped I/O ...
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The lowest 4 bits are hardwired to 1h. The lowest 20 bits of the prefetchable memory base address are assumed 0000h, which results in a natural alignment to ...
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If the prefetchable memory space on the secondary bus resides on top of the 4GB boundary, the prefetchable memory base address upper 32 bit register is set to 0 and the prefetchable memory limit address upper 32 bit register is ...
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Note that PI7C8154B claims VGA palette write transactions by asserting DEVSEL# in VGA snoop mode. When VGA snoop bit is set, PI7C8154B forwards downstream transactions within the 3C6h, 3C8h and 3C9h ...
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PI7C8154B does not combine or merge write transactions: PI7C8154B does not combine separate write transactions into a single write ...
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Pass Delayed Write Request Delayed Read Completion Delayed Write Completion Note: The superscript accompanying some of the table entries refers to any applicable ordering rule listed in this section. Many entries are not governed by these ordering rules; therefore, the ...
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The device signaling the interrupt performs a read of the data just written (software). The device driver performs a read operation to any register in the interrupting device before accessing data written by the device (software). System hardware guarantees that ...
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If parity error response bit is not set, PI7C8154B proceeds normally and accepts transaction directed to or across PI7C8154B. PI7C8154B sets the detected parity error bit in the secondary status register PI7C8154B asserts P_SERR# and sets ...
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For upstream transactions, when PI7C8154B detects a read data parity error on the primary bus, the following events occur: PI7C8154B asserts P_PERR# 2 cycles following the data transfer, if the primary interface parity error response bit is set in the ...
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For downstream transactions, when PI7C8154B is delivering data to the target on the secondary bus and S_PERR# is asserted by the target, the following events occur: PI7C8154B sets the secondary interface data parity detected bit in the secondary status register, ...
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Bridge completes the transaction normally. For upstream transactions, when the parity error is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur: Bridge asserts S_PERR# ...
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Bridge sets the data parity detected bit in the status register, if the parity error response bit is set in the command register of the primary interface. Bridge asserts P_SERR# and sets the signaled system error bit in the status ...
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Secondary Transaction Type Detected Parity Error Bit 0 Read 0 Read 0 Posted Write 0 Posted Write 0 Posted Write 1 Posted Write 0 Delayed Write 0 Delayed Write 0 Delayed Write 1 Delayed Write Note: x=don’t care Table 5-3 ...
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Secondary Transaction Type Detected Parity Detected Bit 0 Posted Write 0 Posted Write 0 Delayed Write 1 Delayed Write 0 Delayed Write 0 Delayed Write Note: x=don’t care Table 5-5 shows assertion of P_PERR#. This signal is set under the ...
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S_PERR# Transaction Type 1 Delayed Write 2 0 Delayed Write 0 Delayed Write Note: x=don’t care 2 =The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. Table 5-7 shows assertion of P_SERR#. ...
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Target abort detected during posted write transaction. Master abort detected during posted write transaction. Posted write data discarded after 2 Parity error reported on target bus during posted write transaction (see previous section) Delayed write data discarded after 2 Delayed ...
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Section 2.7.4. It also samples the lock signal. If there is a lock established between 2 ports or the target bus is already locked by ...
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LOCKED TRANSACTION IN UPSTREAM DIRECTION The bridge ignores upstream lock and transactions. The bridge will pass these transactions as normal transactions without lock established. 6.3 ENDING EXCLUSIVE ACCESS After the lock has been acquired on both initiator and target ...
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PCI bus, the bridge implements an internal arbiter. This arbiter can be disabled, and an external arbiter can be used instead. This chapter describes primary and secondary bus arbitration. 7.1 PRIMARY PCI BUS ARBITRATION The bridge implements a request ...
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Each bus master, including PI7C8154B, can be configured either the low priority group or the high priority group by setting the corresponding priority bit in the arbiter-control register. The arbiter-control register is located at ...
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SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER The internal arbiter is disabled when the secondary bus central function control pin, S_CFN#, is tied HIGH. An external arbiter must then be used. When S_CFN# is tied HIGH, PI7C8154B reconfigures two ...
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GPIO CONTROL REGISTERS During normal operation, the following device specific configuration registers control the GPIO interface: The GPIO output data register The GPIO output enable control register The GPIO input data register These registers consist of five 4-bit fields: ...
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Table 8-1 GPIO OPERATION GPIO Pin GPIO[0] GPIO[1] GPIO[2] GPIO[3] The data is input through the dedicated input signal, MSK_IN. The shift register circuitry is not necessary for correct operation of PI7C8154B. The shift register can be eliminated, and MSK_IN ...
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After the shift operation is complete, the bridge tri-states the GPIO signals and deasserts S_RESET#. PI7C8154B then ignores MSK_IN. Control of the GPIO signal now reverts to PI7C8154B GPIO control registers. The clock disable mask can be modified subsequently through ...
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EEPROM MODE AT RESET During a reset, the bridge will autoload information/data from the EEPROM if the automatic load condition is met. The first offset in the EEPROM contains a signature. If the signature is recognized, the autoload will ...
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EEPROM BYTE ADDRESS 21 – 22h 23 – 24h 25 – 26h 27 – 28h 29 – 2Ah 2Bh 2C – 3Fh 10 VITAL PRODUCT DATA (VPD) The bridge contains the Vital Product Data registers as specified in the PCI ...
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P_M66EN is HIGH and S_M66EN is LOW, the S_CLKOUT[9:0] outputs will be equal to half of the ASYN_CLKIN. The PI7C8154B in asynchronous mode may run in the following frequencies: Table 11-1 VALID ASYNCHRONOUS CLOCK FREQUENCIES Primary (MHz) 25MHz to 66MHz ...
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RESET This chapter describes the primary interface, secondary interface, and chip reset mechanisms. 13.1 PRIMARY INTERFACE RESET PI7C8154B has a reset input, P_RESET#. When P_RESET# is asserted, the following events occur: PI7C8154B immediately tri-states all primary PCI interface signals. ...
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CHIP RESET The chip reset bit in the diagnostic control register can be used to reset the PI7C8154B and the secondary bus. When the chip reset bit is set, all registers and chip state are reset and all signals ...
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CONFIGURATION REGISTERS PCI configuration defines a 64 DWORD space to define various attributes of PI7C8154B as shown below. Table 14-1 CONFIGURATION SPACE MAP 31-24 Device ID Primary Status Reserved Secondary Latency Timer Secondary Status Memory Limit Address Prefetchable Memory ...
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SIGNAL TYPES Signal Type R/O R/W R/WC R/WR R/WS 14.1.2 VENDOR ID REGISTER – OFFSET 00h Bit Function 15:0 Vendor ID 14.1.3 DEVICE ID REGISTER – OFFSET 00h Bit Function 31:16 Device ID 14.1.4 COMMAND REGISTER – OFFSET 04h ...
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Bit Function VGA Palette 5 Snoop Enable Parity Error 6 Response Wait Cycle 7 Control 8 P_SERR# enable Fast Back-to- 9 Back Enable 15:10 Reserved 14.1.5 STATUS REGISTER – OFFEST 04h Bit Function 19:16 Reserved 20 Capabilities List 21 66MHz ...
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Bit Function 27 Signaled Target Abort 28 Received Target Abort 29 Received Master Abort 30 Signaled System Error 31 Detected Parity Error 14.1.6 REVISION ID REGISTER – OFFSET 08h Bit Function 7:0 Revision 14.1.7 CLASS CODE REGISTER – OFFSET 08h ...
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HEADER TYPE REGISTER – OFFSET 0Ch Bit Function 23:16 Header Type 14.1.11 PRIMARY BUS NUMBER REGISTER – OFFSET 18h Bit Function 7:0 Primary Bus Number 14.1.12 SECONDARY BUS NUMBER REGISTER – OFFSET 18h Bit Function 15:8 Secondary Bus Number ...
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Bit Function 7:4 I/O Base Address [15:12] 14.1.16 I/O LIMIT REGISTER – OFFSET 1Ch Bit Function 9:8 32-bit Indicator 11:10 Reserved 15:12 I/O Limit Address [15:12] 14.1.17 SECONDARY STATUS REGISTER – OFFSET 1Ch Bit Function 20:16 Reserved 21 66MHz Capable ...
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Bit Function Detected Parity 31 Error 14.1.18 MEMORY BASE REGISTER – OFFSET 20h Bit Function 3:0 Reserved 15:4 Memory Base Address [15:4] 14.1.19 MEMORY LIMIT REGISTER – OFFSET 20h Bit Function 19:16 Reserved 31:20 Memory Limit Address [31:20] 14.1.20 PREFETCHABLE ...
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PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h Bit Function 19:16 64-bit addressing 31:20 Prefetchable Memory Limit Address [31:20] 14.1.22 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h Bit Function 31:0 Prefetchable Memory Base Address, Upper 32-bits ...
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CAPABILITY POINTER REGISTER – OFFSET 34h Bit Function 7:0 Enhanced Capabilities Port Pointer 14.1.27 INTERRUPT LINE REGISTER – OFFSET 3Ch Bit Function 7:0 Interrupt Line 14.1.28 INTERRUPT PIN REGISTER – OFFSET 3Ch Bit Function 15:8 Interrupt Pin 14.1.29 BRIDGE ...
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Bit Function Type 19 VGA enable R/W 20 Reserved R/O 21 Master Abort R/W Mode 22 Secondary R/W Interface Reset 23 Fast Back-to- R/W Back Enable 24 Primary Master R/W Timeout 25 Secondary R/W Master Timeout 26 Master Timeout R/WC ...
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Bit Function 31-28 Reserved 14.1.30 DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h Bit Function 0 Reserved 1 Memory Write Disconnect Control 3:2 Reserved 4 Secondary Bus Prefetch Disable 5 Live Insertion Mode 7:6 Reserved 8 Chip Reset 15:9 Reserved ...
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Bit Function 26 Broken Master Timeout Enable 27 Automatic Preemption Control 31:28 Reserved 14.1.32 EXTENDED CHIP CONTROL REGISTER – OFFSET 48h Bit Function Memory Read 0 Flow Through Disable 1 Park Downstream ( Memory 2 Read Dynamic Prefetching ...
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Bit Function Memory Read 4 Underflow Control 15:5 Reserved 14.1.33 UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h Bit Function Upstream ( Memory Base and Limit Enable 31:17 Reserved 14.1.34 SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET ...
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EEPROM AUTOLOAD CONTROL / STATUS REGISTER – OFFSET 50h Bit Function 15:0 Reserved EEPROM 16 Autoload Control Fast EEPROM 17 Autoload Control EEPROM 18 Autoload Status 31:19 Reserved 14.1.37 EEPROM ADDRESS / CONTROL REGISTER – OFFSET 54h Bit Function ...
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UPSTREAM ( MEMORY BASE ADDRESS REGISTER – OFFSET 58h Bit Function 64-bit 3:0 Addressing Upstream 15:4 Memory Base 14.1.40 UPSTREAM ( MEMORY LIMIT ADDRESS REGISTER – OFFSET 58h Bit Function 64-bit 19:16 Addressing Upstream 31:20 ...
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Bit Function Type Posted Write 1 R/W with Parity Error Posted Write 2 with Non- R/W Delivery Data Target Abort 3 During Posted R/W Write Master Abort 4 During Posted R/W Write Delayed Write 5 with Non- R/W Delivery Delayed ...
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GPIO DATA AND CONTROL REGISTER – OFFSET 64h Bit Function GPIO output 11:8 write-1-to-clear GPIO output 15:12 write-1-to-set GPIO output 19:16 enable write-1- to-clear GPIO output 23:20 enable write-1- to-set 27:24 Reserved GPIO Input Data 31:28 Register 14.1.45 SECONDARY ...
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Bit Function Type S_CLKOUT[2] 5:4 R/W disable S_CLKOUT[3] 7:6 R/W disable S_CLKOUT[4] 8 R/W disable S_CLKOUT[5] 9 R/W disable S_CLKOUT[6] 10 R/W disable S_CLKOUT[7] 11 R/W disable S_CLKOUT[8] 12 R/W disable S_CLKOUT[9] 13 R/W disable 15:14 Reserved RO Page 93 ...
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P_SERR# STATUS REGISTER – OFFSET 68h Bit Function Address Parity 16 Error Posted Write 17 Data Parity Error Posted Write 18 Non-delivery Target Abort 19 during Posted Write Master Abort 20 during Posted Write Delayed Write 21 Non-delivery Delayed ...
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Bit Function Type Secondary Memory Write 4 R/W Command Alias Enable Primary Memory Read 5 R/W Line/Multiple Alias Enable Secondary Memory Read 6 R/W Line/Multiple Alias Enable Primary Memory Write and 7 Invalidate R/W Command Alias Disable Secondary Memory Write ...
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Bit Function Ordering Rules 13 Control 2 15:14 Reserved 14.1.48 SECONDARY MASTER TIMEOUT COUNTER REGISTER – OFFSET 80h Bit Function Secondary 15:0 Master Timeout 14.1.49 PRIMARY MASTER TIMEOUT COUNTER REGISTER – OFFSET 80h Bit Function Primary Master 31:16 Timeout 14.1.50 ...
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CHASSIS NUMBER REGISTER – OFFSET B0h Bit Function 31:24 Chassis Number 14.1.54 CAPABILITY ID REGISTER – OFFSET DCh Bit Function Enhanced 7:0 Capabilities ID 14.1.55 NEXT ITEM POINTER REGISTER – OFFSET DCh Bit Function Next Item 15:8 Pointer 14.1.56 ...
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Bit Function 12:9 Data Select 14:13 Data Scale 15 PME status 14.1.58 PPB SUPPORT EXTENSIONS REGISTER – OFFSET E0h Bit Function 21:16 Reserved 22 B2_B3 Bus Power/Clock 23 Control Enable 14.1.59 DATA REGISTER – OFFSET E0h Bit Function 31:24 Data ...
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Bit Function PI (Programming 21:20 Interface) EXT (ENUM# 22 Status – Extraction) INS (ENUM# 23 Status – Insertion) 31:24 Reserved 14.1.63 CAPABILITY ID REGISTER – OFFSET E8h Bit Function 7:0 Capability ID 14.1.64 NEXT POINTER REGISTER – OFFSET E8h Bit ...
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BRIDGE BEHAVIOR A PCI cycle is initiated by asserting the FRAME# signal bridge, there are a number of possibilities. Those possibilities are summarized in the table below: 15.1 BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES Initiator Master on ...
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REPORTING PARITY ERRORS For all address phases parity error is detected, the error should be reported on the P_SERR# signal by asserting P_SERR# for one cycle and then tri-stating two cycles after the bad address. P_SERR# can ...
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TAP pins, instruction register, test data registers and TAP controller. Figure 16-1 illustrates how these pieces fit together to form the JTAG unit. Figure 16-1 TEST ACCESS PORT DIAGRAM 16.1.1 TAP PINS The PI7C8154B’s ...
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Upon activation of the TRST# reset pin, the latched instruction asynchronously changes to the id code instruction. When the TAP controller moves into the test state other than by reset activation, the opcode changes as TDI shifts, and becomes active ...
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BYPASS REGISTER The required bypass register, a one-bit shift register, provides the shortest path between TDI and TDO when a bypass instruction is in effect. This allows rapid movement of test data to and from other components on the ...
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Table 16-2 JTAG BOUNDARY REGISTER ORDER Boundary-Scan Register Number ...
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Boundary-Scan Register Pin Name Number 59 S_PAR 60 S_SERR# 61 S_PERR# 62 S_LOCK# 63 S_STOP# 64 S_DEVSEL# 65 S_TRDY# 66 S_IRDY S_FRAME# 69 S_CBE[2] 70 S_AD[16] 71 S_AD[17] 72 S_AD[18] 73 S_AD[19] 74 S_AD[20] 75 S_AD[21] 76 S_AD[22] ...
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Boundary-Scan Register Pin Name Number 121 S_CLKOUT[6] 122 S_CLKOUT[7] 123 S_CLKOUT[8] 124 S_CLKOUT[9] 125 P_RESET# 126 P_GNT# 127 BPCCE 128 P_CLK 129 130 P_REQ# 131 P_AD[31] 132 P_AD[30] 133 P_AD[29] 134 P_AD[28] 135 P_AD[27] 136 P_AD[26] 137 P_AD[25] 138 P_AD[24] ...
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Boundary-Scan Register Pin Name Number 183 P_CBE[6] 184 P_CBE[5] 185 P_CBE[4] 186 P_AD[63] 187 P_AD[62] 188 P_AD[61] 189 P_AD[60] 190 P_AD[59] 191 P_AD[58] 192 P_AD[57] 193 P_AD[56] 194 P_AD[55] 195 P_AD[54] 196 P_AD[53] 197 P_AD[52] 198 P_AD[51] 199 P_AD[50] 200 ...
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ELECTRICAL AND TIMING SPECIFICATIONS 17.1 MAXIMUM RATINGS (Above which the useful life may be impaired. For user guidelines, not tested). Storage Temperature Ambient Temperature with Power Applied Supply Voltage to Ground Potentials (AV Voltage at Input Pins Junction Temperature, ...
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Symbol Parameter Tsu Input setup time to CLK – bused signals Tsu(ptp) Input setup time to CLK – point-to-point Th Input signal hold time from CLK Tval CLK to signal valid delay – bused signals Tval(ptp) CLK to signal valid ...
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GPIO TIMING (66MHZ & 33MHZ) Symbol Parameter T S_CLKIN to GPIO output valid VGPIO T GPIO float to output valid GON T F GPIO active to float delay GOF T GPIO-to-S_CLKIN setup time GSU T GPIO hold time after ...
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PACKAGE INFORMATION 18.1 304-BALL PBGA PACKAGE DIAGRAM Figure 18-1 304-BALL PBGA PACKAGE OUTLINE Thermal characteristics can be found on the web: http://www.pericom.com/packaging/mechanicals.php 18.2 ORDERING INFORMATION Part Number Speed PI7C8154BNAE 66MHz ASYNCHRONOUS 2-PORT Pin – Package 304 – PBGA (Pb-free ...
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APPENDIX PI7C8154/A/B vs. Intel 21154, PBGA-304 19.1 Pericom PI7C8154/A/B provides direct replacement to Intel 21154. Following table is PI7C8154/A/B pin comparison to Intel 21154 Pin Number PI7C8154/A/B A22 VDD / * EEDATA A23 VSS / * EECLK B6 VDD ...
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ASYNCHRONOUS 2-PORT Page 114 of 114 PI7C8154B PCI-to-PCI BRIDGE Advance Information JUNE 2008 REVISION 1.1 ...