PI7C8154BNAIE Pericom Semiconductor, PI7C8154BNAIE Datasheet - Page 31

• Manufacturer Part Number: PI7C8154BNAIE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.7.7
2.8
When the master repeats the transaction and starts transferring prefetchable read data from data
buffers while the read transaction on the target bus is still in progress and before a read boundary is
reached on the target bus, the read transaction starts operating in flow-through mode. Because data
is flowing through the data buffers from the target to the initiator, long read bursts can then be
sustained. In this case, the read transaction is allowed to continue until the initiator terminates the
transaction, or until an aligned 4KB address boundary is reached, or until the buffer fills, whichever
comes first. When the buffer empties, PI7C8154B reflects the stalled condition to the initiator by
disconnecting the initiator with data. The initiator may retry the transaction later if data are needed.
If the initiator does not need any more data, the initiator will not continue the disconnected
transaction. In this case, PI7C8154B will start the master timeout timer. The remaining read data
will be discarded after the master timeout timer expires. To provide better latency, if there are any
other pending data for other transactions in the RDB (Read Data Buffer), the remaining read data
will be discarded even though the master timeout timer has not expired.
PI7C8154B implements a master timeout timer that starts counting when the delayed read
completion is at the head of the delayed transaction queue, and the read data is at the head of the
read data queue. The initial value of this timer is programmable through configuration transaction.
If the initiator does not repeat the read transaction and before the master timeout timer expires (2
default), PI7C8154B discards the read transaction and read data from its queues. PI7C8154B also
conditionally asserts P_SERR# (see Section 5.4).
PI7C8154B has the capability to post multiple delayed read requests, up to a maximum of four in
each direction. If an initiator starts a read transaction that matches the address and read command
of a read transaction that is already queued, the current read command is not posted as it is already
contained in the delayed transaction queue.
See Section 4 for a discussion of how delayed read transactions are ordered when crossing
PI7C8154B.
FAST BACK-TO-BACK TRANSACTIONS
PI7C8154B is capable of decoding fast back-to-back read transactions on both the primary and
secondary. Also, PI7C8154B cannot generate fast back-to-back read transactions on the secondary
or primary even though bit[23] of offset 3Ch is set to ‘1’ or bit[9] of offset 04h is set to ‘1’.
CONFIGURATION TRANSACTIONS
Configuration transactions are used to initialize a PCI system. Every PCI device has a
configuration space that is accessed by configuration commands. All registers are accessible in
configuration space only.
In addition to accepting configuration transactions for initialization of its own configuration space,
the PI7C8154B also forwards configuration transactions for device initialization in hierarchical PCI
systems, as well as for special cycle generation.
To support hierarchical PCI bus systems, two types of configuration transactions are specified:
Type 0 and Type 1.
Type 0 configuration transactions are issued when the intended target resides on the same PCI bus
as the initiator. A Type 0 configuration transaction is identified by the configuration command and
the lowest two bits of the address set to 00b.
Page 31 of 112
ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
PCI-to-PCI BRIDGE
Advance Information
PI7C8154B
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