PI7C8154BNAIE Pericom Semiconductor, PI7C8154BNAIE Datasheet - Page 72

• Manufacturer Part Number: PI7C8154BNAIE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10
11
11.1
11.2
11.3
VITAL PRODUCT DATA (VPD)
The bridge contains the Vital Product Data registers as specified in the PCI Local Bus
Specification, Revision 2.2. The bridge provides 192 bytes of storage in the EEPROM for the VPD
data starting at offset ECh of the configuration space.
CLOCKS
This chapter provides information about the clocks.
PRIMARY AND SECONDARY CLOCK INPUTS
PI7C8154B implements a primary clock input for the PCI interface. The primary interface is
synchronized to the primary clock input, P_CLK, and the secondary interface is synchronized to
the secondary clock input. The secondary clock operates at either the same frequency as the
primary clock, at half of the frequency of the primary clock, or can be derived from the secondary
clock input (ASYNC_CLKIN). PI7C8154B operates at a maximum frequency of 66 MHz. The
secondary interface may run up to 80MHz on the PI7C8154B-80.
SECONDARY CLOCK OUTPUTS
The bridge has 10 secondary clock outputs, S_CLKOUT[9:0], that can be used as clock inputs for
up to nine external secondary bus devices. In synchronous mode (ASYNC_SEL# = 1), the
S_CLKOUT[9:0] outputs are derived from P_CLK. The secondary clock edges are delayed from
P_CLK edges by a minimum of 0ns. In asynchronous mode (ASYNC_SEL# = 0), the
S_CLKOUT[9:0] outputs are derived from ASYNC_CLKIN. These are the rules for using
secondary clocks:
ASYNCHRONOUS MODE
To set the PI7C8154B into asynchronous mode, ASYNC_SEL# must be set to 0. In asynchronous
mode, the S_CLKOUT[9:0] outputs will be derived from ASYNC_CLKIN. Clock division is still
functional based on the setting of the P_M66EN and S_M66EN pins. For example, when
EEPROM BYTE
Each secondary clock output is limited to no more than one load
One of the secondary clock outputs must be used to feedback to S_CLKIN
ADDRESS
29 – 2Ah
2C – 3Fh
21 – 22h
23 – 24h
25 – 26h
27 – 28h
2Bh
CONFIGURATION
DE – DFh
OFFSET
E0 – E1h
74 – 75h
80 – 81h
82 – 83h
E3h
Page 72 of 114
Port Option Register
Secondary Master Timeout Counter
Primary Master Timeout Counter
Power Management Capabilities
Power Management Data
DESCRIPTION
Power Management Control Status Register
Reserved – MUST BE SET TO 0
ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
PCI-to-PCI BRIDGE
Advance Information
PI7C8154B