PI7C8154BNAIE Pericom Semiconductor, PI7C8154BNAIE Datasheet - Page 101

• Manufacturer Part Number: PI7C8154BNAIE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.2.3
15.2.4
16
16.1
REPORTING PARITY ERRORS
For all address phases, if a parity error is detected, the error should be reported on the P_SERR#
signal by asserting P_SERR# for one cycle and then tri-stating two cycles after the bad address.
P_SERR# can only be asserted if bit 6 and 8 in the Command Register are both set to 1. For write
data phases, a parity error should be reported by asserting the P_PERR# signal two cycles after the
data phase and should remain asserted for one cycle when bit 6 in the Command register is set to a
1. The target reports any type of data parity errors during write cycles, while the master reports data
parity errors during read cycles.
Detection of an address parity error will cause the PCI-to-PCI Bridge target to not claim the bus
(P_DEVSEL# remains inactive) and the cycle will then terminate with a Master Abort. When the
bridge is acting as master, a data parity error during a read cycle results in the bridge master
initiating a Master Abort.
SECONDARY IDSEL MAPPING
When PI7C8154B detects a Type 1 configuration transaction for a device connected to
the secondary, it translates the Type 1 transaction to Type 0 transaction on the downstream
interface. Type 1 configuration format uses a 5-bit field at P_AD[15:11] as a device number. This
is translated to S_AD[31:16] by PI7C8154B.
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER
An IEEE 1149.1 compatible Test Access Port (TAP) controller and associated TAP pins are
provided to support boundary scan in PI7C8154B for board-level continuity test and diagnostics.
The TAP pins assigned are TCK, TDI, TDO, TMS and TRST#. All digital input, output,
input/output pins are tested except TAP pins.
The IEEE 1149.1 Test Logic consists of a TAP controller, an instruction register, and
a group of test data registers including Bypass and Boundary Scan registers. The TAP controller is
a synchronous 16-state machine driven by the Test Clock (TCK) and the Test Mode Select (TMS)
pins. An independent power on reset circuit is provided to ensure the machine is in
TEST_LOGIC_RESET state at power-up. The JTAG signal lines are not active when the PCI
resource is operating PCI bus cycles.
PI7C8154B implements 3 basic instructions: BYPASS, SAMPLE/PRELOAD, and EXTEST.
BOUNDARY SCAN ARCHITECTURE
Boundary-scan test logic consists of a boundary-scan register and support logic. These are accessed
through a Test Access Port (TAP). The TAP provides a simple serial interface that allows all
processor signal pins to be driven and/or sampled, thereby providing direct control and monitoring
of processor pins at the system level.
This mode of operation is valuable for design debugging and fault diagnosis since it permits
examination of connections not normally accessible to the test system. The following subsections
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ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
PCI-to-PCI BRIDGE
Advance Information
PI7C8154B