PI7C8154BNAIE Pericom Semiconductor, PI7C8154BNAIE Datasheet - Page 90

• Manufacturer Part Number: PI7C8154BNAIE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.39
14.1.40
14.1.41
14.1.42
14.1.43
UPSTREAM (S TO P) MEMORY BASE ADDRESS REGISTER – OFFSET
58h
UPSTREAM (S TO P) MEMORY LIMIT ADDRESS REGISTER – OFFSET
58h
UPSTREAM (S TO P) MEMORY BASE ADDRESS UPPER 32-BIT
REGISTER – OFFSET 5Ch
UPSTREAM (S TO P) MEMORY LIMIT ADDRESS UPPER 32-BIT
REGISTER – OFFSET 60h
P_SERR# EVENT DISABLE REGISTER – OFFSET 64h
Bit
3:0
15:4
Bit
19:16
31:20
Bit
31:0
Bit
31:0
Bit
0
Function
64-bit
Addressing
Upstream
Memory Base
Function
64-bit
Addressing
Upstream
Memory Limit
Function
Upstream
Memory Base
Upper 32-bits
Function
Upstream
Memory Base
Upper 32-bits
Function
Reserved
Type
R/O
R/W
Type
R/O
R/W
Type
R/W
Type
R/W
Type
R/O
Page 90 of 114
Description
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 0
Defines the bottom address of an address range used by the bridge to
determine when to forward upstream memory transactions.
Reset to 0
Description
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 0
Defines the top address of an address range used by the bridge to
determine when to forward upstream memory transactions.
Reset to 0
Description
Defines the upper 32-bits of a 64-bit bottom address of an address range
for the bridge to determine when to forward upstream memory read and
write transactions.
Reset to 0
Description
Defines the upper 32-bits of a 64-bit top address of an address range for
the bridge to determine when to forward upstream memory read and write
transactions.
Reset to 0
Description
Returns 0 when read. Reset to 0
ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
PCI-to-PCI BRIDGE
Advance Information
PI7C8154B