PI7C8154BNAIE Pericom Semiconductor, PI7C8154BNAIE Datasheet - Page 46

• Manufacturer Part Number: PI7C8154BNAIE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.3
3.3.1
Accordingly, if the ISA enable bit is set, PI7C8154B forwards upstream those I/O transactions
addressing the top 768 bytes of each aligned 1KB block within the first 64KB of I/O space. The
master enable bit in the command configuration register must also be set to enable upstream
forwarding. All other I/O transactions initiated on the secondary bus are forwarded upstream only if
they fall outside the I/O address range.
When the ISA enable bit is set, devices downstream of PI7C8154B can have I/O space mapped into
the first 256 bytes of each 1KB chunk below the 64KB boundary, or anywhere in I/O space above
the 64KB boundary.
MEMORY ADDRESS DECODING
PI7C8154B has three mechanisms for defining memory address ranges for forwarding of memory
transactions:
This section describes the first two mechanisms. Section 3.4.1 describes VGA mode. To enable
downstream forwarding of memory transactions, the memory enable bit must be set in the
command register in configuration space. To enable upstream forwarding of memory transactions,
the master-enable bit must be set in the command register. The master-enable bit also allows
upstream forwarding of I/O transactions if it is set.
CAUTION
If any configuration state affecting memory transaction forwarding is changed by a configuration
write operation on the primary bus at the same time that memory transactions are ongoing on the
secondary bus, response to the secondary bus memory transactions is not predictable. Configure
the memory-mapped I/O base and limit address registers, prefetchable memory base and limit
address registers, and VGA mode bit before setting the memory enable and master enable bits, and
change them subsequently only when the primary and secondary PCI buses are idle.
MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS
Memory-mapped I/O is also referred to as non-prefetchable memory. Memory addresses that
cannot automatically be pre-fetched but that can be conditionally pre-fetched based on command
type should be mapped into this space. Read transactions to non-prefetchable space may exhibit
side effects; this space may have non-memory-like behavior. PI7C8154B prefetches in this space
only if the memory read line or memory read multiple commands are used; transactions using the
memory read command are limited to a single data transfer.
The memory-mapped I/O base address and memory-mapped I/O limit address registers define an
address range that PI7C8154B uses to determine when to forward memory commands. PI7C8154B
forwards a memory transaction from the primary to the secondary interface if the transaction
address falls within the memory-mapped I/O address range. PI7C8154B ignores memory
transactions initiated on the secondary interface that fall into this address range. Any transactions
that fall outside this address range are ignored on the primary interface and are forwarded upstream
from the secondary interface (provided that they do not fall into the prefetchable memory range or
are not forwarded downstream by the VGA mechanism).
Memory-mapped I/O base and limit address registers
Prefetchable memory base and limit address registers
VGA mode
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ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
PCI-to-PCI BRIDGE
Advance Information
PI7C8154B