PI7C8154BNAIE Pericom Semiconductor, PI7C8154BNAIE Datasheet - Page 88

• Manufacturer Part Number: PI7C8154BNAIE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.33
14.1.34
14.1.35
UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h
SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER –
OFFSET 4Ch
HOT SWAP SWITCH TIME SLOT REGISTER – OFFSET 4Ch
Bit
4
15:5
Bit
16
31:17
Bit
31:28
Bit
27:0
Function
Memory Read
Underflow
Control
Reserved
Function
Upstream (S to
P) Memory Base
and Limit Enable
Reserved
Function
Secondary bus
arbiter
preemption
contorl
Function
Hot Swap Switch
Time Slot
Register
Type
R/W
R/O
Type
R/W
R/O
Type
R/W
Type
R/W
Page 88 of 114
Description
0: Bridge will start returning memory read data to the source bus after the
2
(underflow), bridge will insert target wait states (up to 7 wait states) on
the source bus and prefetch more data in the data buffer. If there is no
further data coming into the data buffer and the number of wait states
reaches 7, the bridge will assert STOP# to disconnect the master and
terminate the transaction.
1: Bridge will not start returning memory read data to the source bus until
1 cache line of data is accumulated in the data buffer. If the data buffer is
read as empty (underflow), the bridge will stop prefetching at the
destination bus and signal a disconnect to the external master on the
source bus. The transaction entry and the associated data will be
discarded.
Reset to 0
Returns 0 when read. Reset to 0.
Description
0: Upstream memory range is the entire range except the downstream
memory channel
1: Upstream memory range is confined to the upstream Memory Base and
Limit
*see Offset 58h, 5Ch, and 60h for upstream memory range
Returns 0 when read. Reset to 0.
Description
Controls the number of clock cycles after frame is asserted before
preemption is enabled.
1xxx: Preemption off
0000: Preemption enabled after 0 clock cycles after FRAME asserted
0001: Preemption enabled after 1 clock cycle after FRAME asserted
0010: Preemption enabled after 2 clock cycles after FRAME asserted
0011: Preemption enabled after 4 clock cycles after FRAME asserted
0100: Preemption enabled after 8 clock cycles after FRAME asserted
0101: Preemption enabled after 16 clock cycles after FRAME asserted
0110: Preemption enabled after 32 clock cycles after FRAME asserted
0111: Preemption enabled after 64 clock cycles after FRAME asserted
Description
Hot Swap switch time slot set to 0003A98h (15K PCI clocks).
Reset to 0003A98h.
nd
data is in the data buffer. If the data buffer is read as empty
ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
PCI-to-PCI BRIDGE
Advance Information
PI7C8154B