PI7C8154BNAIE Pericom Semiconductor, PI7C8154BNAIE Datasheet - Page 79

• Manufacturer Part Number: PI7C8154BNAIE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.6
14.1.7
14.1.8
14.1.9
REVISION ID REGISTER – OFFSET 08h
CLASS CODE REGISTER – OFFSET 08h
CACHE LINE SIZE REGISTER – OFFSET 0Ch
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch
Bit
27
28
29
30
31
Bit
7:0
Bit
15:8
23:16
31:24
Bit
7:0
Bit
15:8
Function
Signaled Target
Abort
Received Target
Abort
Received Master
Abort
Signaled System
Error
Detected Parity
Error
Function
Revision
Function
Programming
Interface
Sub-Class Code
Base Class Code
Function
Cache Line Size
Function
Primary Latency
timer
Type
R/WC
R/WC
R/WC
R/WC
R/WC
Type
R/O
Type
R/O
R/O
R/O
Type
R/W
Type
R/W
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Description
0: Bridge does not signal target abort on the primary interface
1: Bridge signals target abort on the primary interface
Reset to 0
0: Bridge does not detect target abort on the primary interface
1: Bridge detects target abort on the primary interface
Reset to 0
0: Bridge does not detect master abort on the primary interface
1: Bridge detects master abort on the primary interface
Reset to 0
0: Bridge does not assert SERR# on the primary interface
1: Bridge asserts SERR# on the primary interface
Reset to 0
0: Address of data parity error not detected by the bridge on the primary
interface
1: Address of data parity error detected by the bridge on the primary
interface
Reset to 0
Description
Indicates revision number of device. Hardwired to 02h
Description
Read as 0 to indicate no programming interfaces have been defined for
PCI-to-PCI bridges
Read as 04h to indicate device is PCI-to-PCI bridge
Read as 06h to indicate device is a bridge device
Description
Designates the cache line size for the system and is used when
terminating memory write and invalidate transactions and when
prefetching memory read transactions.
Only cache line sizes (in units of 4-byte) which are a power of two are
valid (only one bit can be set in this register; only 00h, 01h, 02h, 04h,
08h, and 10h are valid values).
Reset to 0
Description
This register sets the value for the Master Latency Timer, which starts
counting when the master asserts FRAME#.
Reset to 0
ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
PCI-to-PCI BRIDGE
Advance Information
PI7C8154B