MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 92

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Enhanced Multiply-Accumulate Unit (EMAC)
As with change or use stalls between accumulators and general-purpose registers, introducing intervening
instructions that do not reference the busy register can reduce or eliminate sequence-related store-MAC
instruction stalls. A major benefit of the EMAC is the addition of three accumulators to minimize stalls
caused by exchanges between accumulator(s) and general-purpose registers.
3.3.4
MACSR[S/U,F/I] selects one of the following three modes, where each mode defines a unique operand
type:
This format can represent numbers in the range -1 < operand < 1 - 2
For words and longwords, the largest negative number that can be represented is -1, whose internal
representation is 0x8000 and 0x8000_0000, respectively. The largest positive word is 0x7FFF or (1 - 2
the most positive longword is 0x7FFF_FFFF or (1 - 2
3.3.5
MAC opcodes are described in the ColdFire Programmer’s Reference Manual.
Remember the following:
3-14
1. Two’s complement signed integer: In this format, an N-bit operand value lies in the range -2
2. Unsigned integer: In this format, an N-bit operand value lies in the range 0 < operand < 2
3. Two’s complement, signed fractional: In an N-bit number, the first bit is the sign bit. The remaining
•
•
•
< operand < 2
binary point is right of the lsb.
bits signify the first N-1 bits after the binary point. Given an N-bit number, a
its value is given by the equation in
Unless otherwise noted, the value of MACSR[N,Z] is based on the result of the final operation that
involves the product and the accumulator.
The overflow (V) flag is managed differently. It is set if the complete product cannot be represented
as a 40-bit value (this applies to 32 × 32 integer operations only) or if the combination of the
product with an accumulator cannot be represented in the given number of bits. The EMAC design
includes an additional product/accumulation overflow bit for each accumulator that are treated as
sticky indicators and are used to calculate the V bit on each MAC or MSAC instruction. See
Section 3.2.1, “MAC Status Register
For the MAC design, the assembler syntax of the MAC (multiply and add to accumulator) and
MSAC (multiply and subtract from accumulator) instructions does not include a reference to the
single accumulator. For the EMAC, assemblers support this syntax and no explicit reference to an
accumulator is interpreted as a reference to ACC0. Assemblers also support syntaxes where the
destination accumulator is explicitly defined.
Data Representation
MAC Opcodes
(N-1)
- 1. The binary point is right of the lsb.
value
=
–
(
1 a
⋅
Equation
N 1
(MACSR)”.
–
)
+
N 2
i
∑
=
–
3-3.
0
-31
2
–
).
(
i
+
1 N
–
)
⋅
ai
(N-1)
.
N-1
Freescale Semiconductor
a
N-2
a
N-3
... a
N
- 1. The
Eqn. 3-3
2
a
(N-1)
-15
1
a
0
);
,