MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 262
MCF5282CVM66
Manufacturer Part Number
MCF5282CVM66
Description
Manufacturer
Freescale
Datasheet
1.MCF5282CVM66.pdf
(766 pages)
Specifications of MCF5282CVM66
Cpu Family
MCF528x
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Interface Type
CAN/I2C/QSPI/UART
Total Internal Ram Size
64KB
# I/os (max)
150
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
3.3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
MA-BGA
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
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Signal Descriptions
14.2.2.5 SDRAM Clock Enable (SCKE)
This output is the SDRAM clock enable.
This pin is configured as GPIO PSD0 in single-chip mode.
14.2.3
The clock and reset signals configure the device and provide interface signals to the external system.
14.2.3.1 Reset In (RSTI)
Asserting RSTI causes the device to enter reset exception processing. When RSTI is recognized the
address bus, data bus, SIZ, R/W, AS, and TS are three-stated. RSTO is asserted automatically when RSTI
is asserted.
14.2.3.2 Reset Out (RSTO)
After RSTI is asserted, the PLL temporarily loses its lock, during which time RSTO is asserted. When the
PLL regains its lock, RSTO negates again. This signal can be used to reset external devices.
14.2.3.3 EXTAL
This input is driven by an external clock except when used as a connection to the external crystal when
using the internal oscillator.
14.2.3.4 XTAL
This output is an internal oscillator connection to the external crystal.
14.2.3.5 Clock Output (CLKOUT)
The internal PLL generates CLKOUT. This output reflects the internal system clock.
14.2.4
14.2.4.1 RCON
If the external RCON signal is asserted, then various chip functions, including the reset configuration pin
functions after reset, are configured according to the levels driven onto the external data pins (see
Section 27.6, “Functional
on the external configuration pins to allow for module configuration.
14.2.4.2 CLKMOD[1:0]
The state of the CLKMOD[1:0] pins during reset determines the clock mode after reset.
14-22
Clock and Reset Signals
Chip Configuration Signals
Description”). The internal configuration signals are driven to reflect the levels
Freescale Semiconductor
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