MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 154

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

System Control Module (SCM)
8.3
The memory map for the SCM registers is shown in
memory-mapped as offsets within the 1 Gbyte IPS address space and accesses are controlled to these
registers by the control definitions programmed into the SACU.
8.4
8.4.1
The IPSBAR specifies the base address for the 1 Gbyte memory space associated with the on-chip
peripherals. At reset, the base address is loaded with a default location of 0x4000_0000 and marked as
valid (IPSBAR[V]=1). If desired, the address space associated with the internal modules can be moved by
loading a different value into the IPSBAR at a later time.
If an address “hits” in overlapping memory regions, the following priority is used to determine what
memory is accessed:
8-2
1. IPSBAR
2. RAMBAR
3. Cache
4. SDRAM
Memory Map and Register Definition
Register Descriptions
Internal Peripheral System Base Address Register (IPSBAR)
Accessing reserved IPSBAR memory space could result in an unterminated
bus cycle that causes the core to hang. Only a hard reset will allow the core
to recover from this state. Therefore, all bus accesses to IPSBAR space
should fall within a module’s memory map space.
1
0x00_000C
0x00_001C
0x00_003C
0x00_0000
0x00_0004
0x00_0008
0x00_0010
0x00_0018
0x00_0020
0x00_0024
0x00_0028
0x00_0030
0x00_0034
0x00_0038
0x00_002c
IPSBAR
The LPICR is described in
Offset
GPACR0
[31:24]
PACR0
PACR4
PACR7
CRSR
MPR
—
—
—
Table 8-1. SCM Register Map
Chapter 7, “Power
GPACR1
[23:16]
CWCR
PACR1
NOTE
—
—
—
—
—
RAMBAR
IPSBAR
MPARK
Management."
—
—
—
Table
LPICR
PACR2
PACR5
PACR8
[15:8]
8-1. All the registers in the SCM are
—
—
—
—
—
1
PACR3
PACR6
CWSR
[7:0]
—
—
—
—
—
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